Design of a VLSI Decoder for Partially Structured LDPC Codes

<table class="table-group" id="tab2"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr class="thead"><td align="left">Code rate</td><td align="center">Staircase</td><td align="center">Pattern</td><td align="center">Free</td></tr><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td align="left"><span style="width: 23.450001px;"><svg height="14.85" id="M18" style="vertical-align:-2.22495pt" version="1.1" viewbox="0 0 23.450001 14.85" width="23.450001" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,12.012)"><path d="M384 0h-275v27q67 5 81.5 18.5t14.5 68.5v385q0 38 -7.5 47.5t-40.5 10.5l-48 2v24q85 15 178 52v-521q0 -55 14.5 -68.5t82.5 -18.5v-27z" id="x31"></path></g><g transform="matrix(.017,-0,0,-.017,8.222,12.012)"><path d="M368 703l-264 -866h-60l265 866h59z" id="x2F"></path></g><g transform="matrix(.017,-0,0,-.017,15.225,12.012)"><path d="M285 378v-2q65 -13 102 -54.5t37 -97.5q0 -57 -30.5 -104.5t-74 -75t-85.5 -42t-72 -14.5q-31 0 -59.5 11t-40.5 23q-19 18 -16 36q1 16 23 33q13 10 24 0q58 -51 124 -51q55 0 88 40t33 112q0 64 -39 96.5t-88 32.5q-29 0 -64 -11l-6 29q77 25 118 57.5t41 84.5
q0 45 -26.5 69.5t-68.5 24.5q-67 0 -120 -79l-20 20l43 63q51 56 127 56h1q66 0 107 -37t41 -95q0 -42 -31 -71q-22 -23 -68 -54z" id="x33"></path></g>
</svg></span></td><td align="center">0.400</td><td align="center">0.467</td><td align="center">0.133</td></tr><tr><td align="left"><span style="width: 23.450001px;"><svg height="14.85" id="M19" style="vertical-align:-2.22495pt" version="1.1" viewbox="0 0 23.450001 14.85" width="23.450001" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,12.012)"><path d="M384 0h-275v27q67 5 81.5 18.5t14.5 68.5v385q0 38 -7.5 47.5t-40.5 10.5l-48 2v24q85 15 178 52v-521q0 -55 14.5 -68.5t82.5 -18.5v-27z" id="x31"></path></g><g transform="matrix(.017,-0,0,-.017,8.222,12.012)"><path d="M368 703l-264 -866h-60l265 866h59z" id="x2F"></path></g><g transform="matrix(.017,-0,0,-.017,15.225,12.012)"><path d="M412 140l28 -9q0 -2 -35 -131h-373v23q112 112 161 170q59 70 92 127t33 115q0 63 -31 98t-86 35q-75 0 -137 -93l-22 20l57 81q55 59 135 59q69 0 118.5 -46.5t49.5 -122.5q0 -62 -29.5 -114t-102.5 -130l-141 -149h186q42 0 58.5 10.5t38.5 56.5z" id="x32"></path></g>
</svg></span></td><td align="center">0.296</td><td align="center">0.519</td><td align="center">0.185</td></tr><tr><td align="left"><span style="width: 23.450001px;"><svg height="14.85" id="M20" style="vertical-align:-2.22495pt" version="1.1" viewbox="0 0 23.450001 14.85" width="23.450001" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,12.012)"><path d="M412 140l28 -9q0 -2 -35 -131h-373v23q112 112 161 170q59 70 92 127t33 115q0 63 -31 98t-86 35q-75 0 -137 -93l-22 20l57 81q55 59 135 59q69 0 118.5 -46.5t49.5 -122.5q0 -62 -29.5 -114t-102.5 -130l-141 -149h186q42 0 58.5 10.5t38.5 56.5z" id="x32"></path></g><g transform="matrix(.017,-0,0,-.017,8.222,12.012)"><path d="M368 703l-264 -866h-60l265 866h59z" id="x2F"></path></g><g transform="matrix(.017,-0,0,-.017,15.225,12.012)"><path d="M285 378v-2q65 -13 102 -54.5t37 -97.5q0 -57 -30.5 -104.5t-74 -75t-85.5 -42t-72 -14.5q-31 0 -59.5 11t-40.5 23q-19 18 -16 36q1 16 23 33q13 10 24 0q58 -51 124 -51q55 0 88 40t33 112q0 64 -39 96.5t-88 32.5q-29 0 -64 -11l-6 29q77 25 118 57.5t41 84.5
q0 45 -26.5 69.5t-68.5 24.5q-67 0 -120 -79l-20 20l43 63q51 56 127 56h1q66 0 107 -37t41 -95q0 -42 -31 -71q-22 -23 -68 -54z" id="x33"></path></g>
</svg></span></td><td align="center">0.182</td><td align="center">0.606</td><td align="center">0.212</td></tr><tr class="table-tr"><td colspan="4"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

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tab2

Table 2

Table 2: Design of a VLSI Decoder for Partially Structured LDPC Codes 