Research Article | Open Access
A Discrete-Time Downsampling FIR Filter for Windowed Integration Samplers
A novel technique to reduce die area on a discrete-time 2 filter for charge sampling is proposed. An SNR comparison of the conventional and the proposed topology reveals that the new technique saves 25% die area occupied by the sampling capacitors of the filter. The idea is also extended to implement higher downsampling factors, and greater percentage of area is saved as the downsampling factor is increased. The proposed filter also has the topological advantage over previously reported works of allowing the designers to use active integration to charge the capacitance, which is critical in obtaining high linearity.
THE need for integration of multiple wireless standards on a single handset calls for the development of a flexible receiver architecture, more popularly known as Software Defined Radio (SDR). Mitola  defined the SDR as a receiver that digitizes all the channels that are incident on the antenna so that all the radio functions can be programmed in a digital signal processor. Although very idealistic in principle, the SDR concept has led to numerous advances in CMOS transceiver design. Key building blocks in the design of this new generation of SDR receivers are the antialising filter and ADC. The choice of the antialiasing filter plays a fundamental role in the requirements on the ADC. For instance, in  the channel of interest has to be down-converted to zero IF and an antialiasing filter is required before baseband voltage sampling in order to isolate the wanted channel from a multitude of unwanted channels. Taking into consideration the bandwidths and blocker profiles of different standards, it is difficult to reconfigure an analog antialiasing filter to meet the wide range of requirements. The inherent antialiasing filtering provided by the windowed integration operation in charge sampling takes advantage of the frequency response nulls to eliminated unwanted interference. References [3–5] are other examples of receivers using charge sampling techniques.
The initial sampling rate for the windowed integration sampler is determined by the stop-band attenuation required for antialiasing and it can be much higher than the Nyquist rate for the input signal. To reduce the sampling rate to the Nyquist rate or the oversampled rate depending on the ADC architecture, downsampling operation has to be performed. After downsampling, the spectrum folds back again with the new sampling frequency equaling the sampling rate divided by the downsampling factor. The antialiasing specification now needs to be met at the multiples of this new sampling frequency. A simple approach is to create a downsampling filter, which can be achieved by just summing up previous samples on capacitors and reading them out simultaneously. However, the attenuation provided by downsampling might not be sufficient and better filtering is necessary. By weighting previous samples with appropriate factors prior to summing up operation, and downsampling filters can be created [2, 3]. These filters provide much deeper and wider nulls at the sampling frequency but require a large number of switches and capacitors. In multi-standard applications, many filters may be needed to select the channels of interest. Optimizing the filters area becomes critical in lowering the production cost.
In this paper, a novel topology for the implementation of a filter with a downsampling factor of two is proposed and compared to the conventional topology adopted in [2, 3]. The proposed topology requires less number of switches and capacitors. To get the same SNR performance, the proposed topology requires 25% less die area for the sampling capacitors. The proposed topology also allows for the implementation of the filter using an active-integrator based sampler, which is difficult in previously proposed topologies. This has the advantage of improved overall linearity and insensitivity to output impedance of the Gm-stage.
The organization of the paper is as follows. The theory of discrete-time downsampling filters and its implementation with conventional topology is explained in Section 2. The proposed filter is introduced in Section 3 and it is compared with the conventional topology. In Section 4, the extension of the proposed filter to get higher downsampling factor is explained. In Section 5, the circuit level simulations of both the topologies are illustrated and the results are compared. The conclusions are provided in Section 6.
2. Discrete-Time Downsampling Filters for Charge Sampling
2.1. Theory of Discrete-Time Downsampling Filters
Windowed integration of current signal on a capacitor for a time , reading out the charge, and discharging the capacitor after each readout is equivalent to filtering the signal and sampling it at . A narrowband signal centered at DC, surrounded by unwanted signals, when sampled at , the unwanted signals around , gets aliased to the signal of interest. This is taken care of in windowed integration by the nulls which occur at multiples of due to filtering. These nulls however offer limited attenuation as the interference bandwidth increases. The attenuation due to filtering, for a bandwidth at null is given by 
In order to meet the attenuation specification for a particular standard, the sampling frequency needs to be very high. Since the design of the ADC would pose extremely challenging specifications at such a high frequency, the sampled signal need to be down-sampled before digitization.
Downsampling causes spectral folding that in turn results in aliasing. The sampled signals which are now stored as charges on capacitors can be down-sampled by adding the current charge-sample with previous samples (Figure 1). This operation gives rise to a moving sum FIR filter that takes care of aliasing, followed by N operation. Equation (2) shows the -domain transfer function and the magnitude response of the filter, respectively,
has nulls at , where varies from to . The attenuation provided by such a filter may not be sufficient for many applications and there is a need for a better filter. Instead of rectangular windowing, if triangular windowing is applied, the following results are obtained for the transfer function of the filter and frequency response, respectively:
The magnitude response is the square of that obtained for moving sum. This gives rise to a better null attenuation compared to the previous case. The disadvantage is that samples are needed to obtain N. Unlike rectangular windows, triangular windows have to overlap in order to give the required performance, making the implementation complex. Triangular windowing for 4 is explained in Figure 2.
2.2. A Note on Frequency Response
In some work [2, 3], discrete time triangular windowing is described as filtering. This is often misleading as the response is and not . For , it is and not . Thus, it is more appropriate to call the filter than . For a sampling frequency of 500?MHz, Figure 3 compares the frequency response of discrete time rectangular windowing, discrete time triangular windowing and for 2 and 4 up to . It should be noted that triangular windowing has better null attenuation compared to rectangular windowing. As triangular windowing approximately follows until , such filters can be called as filters.
2.3. Sinc2?2 Downsampling Filter: Conventional Topology
The conventional topology of downsampling filter [2, 3] is shown in Figure 4. Figure 5 shows its clock scheme. The capacitor discharge switches are not shown for simplification. The sampling rate at the output is chosen to be 250?MHz.
The signal current is integrated for a time window of 2?ns on each capacitor pair. The signal charge, integrated in phase and on a single unit capacitor , and on two unit capacitors during is read out during phase . Similarly, the charge during , and is read out during . A total of four capacitors are connected together and readout simultaneously during each sampling phase. As the signal is sampled already, the filter function can be written in -domain as
The factor 1/4 comes from the fact that four unit capacitors are connected together during readout. The integration for 2?ns will create a filter with first null at 500?MHz. The filter magnitude response for is where which will have two zeros at .
The operation of the filter is explained in Figure 6. The overall filter response will be a cascade of the two filter responses mentioned before and is plotted in Figure 7. The wider nulls at 250?MHz, 750?MHz and so on, are due to the filter magnitude response as explained before.
3. Proposed Topology
3.1. Operation of the Filter
The proposed topology for the downsampling filter is shown in Figure 8 along with the clock diagram. An extra overlap capacitor, is added along with the sampling capacitors . The size of the overlap capacitor is equal to that of the sampling capacitor. The operation of the filter is as follows. During first 2?ns, the current is integrated on and . For the next 2?ns, the overlap capacitor is disconnected while the sampling capacitor continues to integrate the charge. As the capacitance seen by the transconductor is now half the value compared to first 2?ns, the voltage gain is now doubled. In the meantime, is connected to the other sampling capacitor for readout and discharge. The same process is carried out on the other sampling capacitor and the overlap capacitor reconnects to the first sampling capacitor for readout. Switches and discharge the sampling capacitors after readout through switches and .
Effectively, the integration window in steady state looks like a stepwise approximation of a triangular window as shown in Figure 9. The filter response of such a window can be easily plotted and it is a very good match with the response of the conventional filter shown in Figure 7.
3.2. Comparison of Performance of the Two Filters
3.2.1. Area Savings
For both filter topologies, the size of the unit sampling capacitor is determined by the noise requirements at the output. For the same peak to peak voltage range and the same SNR specification, the relation between the sampling capacitor size and transconductance value of the topologies can be determined.
The total integrated noise of the windowed integration sampling circuit is given by  where is the integration window duration. This expression holds under the condition that , where is the output impedance of the transconductor. In the expression for channel noise of MOS device, used in (5), is assumed to be 1 for simplicity. The gain of the sampling circuit is given as .
and denote the transconductance and sampling capacitor values of the conventional topology and and for the proposed topology, respectively.
To get the same SNR, the signal gain and overall noise of both the samplers should be the same. If the noise is reduced by increasing the capacitance, then needs to be increased proportionally to keep the gain and hence the output peak to peak range constant. From the noise expression, it can be seen that, integrated output noise is inversely proportional to square of the sampling capacitor and proportional to . Therefore, the total noise reduces and overall SNR increases.
In the conventional topology, three windows of 2?ns are added together with a scaling factor of 1/4 due to charge sharing. It can be seen that only half of the current is integrated on each sampling capacitor. This means that the effective transconductance for each capacitor will be half of the actual value, that is, :
In case of our proposed topology, the signal integrates on for the first 2?ns, then integrates on for the next 2?ns and finally again integrates on for the last 2?ns. A factor of 1/2 is introduced during the readout operation. Therefore,
Similarly the noise for each topology can be calculated as,
The factor of 16 here is the square of the gain 1/4.
The total area in the conventional filter is (Figure 4), whereas it is only (Figure 8) for the proposed filter. Therefore, 25% of the area from the dominant area consuming factor, the sampling capacitors, can be saved in the proposed filter when compared to the conventional filter.
3.2.2. Benefit of Linearity in Proposed Topology
The basic passive integrator consisting of just an integrator driving a capacitor has some certain disadvantages. In addition to sampling capacitor , it has parasitic capacitance (Figure 10(a)), which is the result of parasitic diodes, overlaps, crossings, strays and fringing effects . The voltage dependence of the parasitic capacitance makes the response sensitive to power supply variations and degrades the distortion performance [7, 8]. Also, the finite output impedance of the Gm stage gets modulated by the swing of the voltage signal at its output. This creates nonlinearity in the overall performance.
The above mentioned problem can be dealt with by using an active integrator based sampler as shown in Figure 10(b) at the cost of power consumption and complexity.
For , the effect of and is neglected. The use of an active integrator can be well justified for use in the application discussed in this paper. Here the signal is at baseband where the above benefits can be obtained without spending so much power. In charge sampling circuits, usually a buffer is required before the ADC to drive low impedance. Here the OTA provides driving capability and hence the output can be read out directly at the sampling capacitor. Figure 11 shows the block diagram of sinc2?2 filter implemented with active integrator and Figure 8(b) shows its clock scheme. In Figure 11, and denote the input and output common voltages of the OTA used for active integration, respectively.
The benefits of active integration are obtained in the proposed topology only because the current is integrated at and read out from only two nodes. This is applicable for any order of decimation filter in the proposed topology. In the conventional topology, current is integrated and read out from multiple capacitors and depending on the order of decimation, it varies. This complicates the active integration implementation and increases power consumption.
4. Extension of the Proposed Topology to Achieve a Higher Downsampling Factor
There are cases where it is needed to integrate and sample the signal at a very high frequency to achieve the required null attenuation. In such a case, it is necessary to down-sample by a higher factor. In this section, the implementation of sinc2N filter using the proposed topology is discussed and compared with the conventional topology.
The conventional topology for the implementation of sinc2N is just a straight forward extension of sinc22 (Figure 4). Figure 12 shows sinc24 filter and its clock scheme. The clock scheme of readout switches & and discharge switches & is not shown in the figure. The sinc2N filter using the proposed topology is shown in Figure 13. Here the capacitors have to satisfy the following equations:
The proposed and the conventional topologies can be compared in the same way as done in Section 3, to obtain
Proceeding in the same way as Section 3, from noise calculations, it can be shown that
The total area required by the two filters is
From (19), it can be noted that as the decimation factor is increased, the percentage of area saved compared to the conventional topology also increases. For large values of N, the area savings rapidly approaches 50%.
Prototype filters of the conventional and proposed technique are simulated in 45?nm technology and the results are compared. A differential version of the filter is shown in Figure 14. A PMOS input fully differential folded cascode structure with active common mode feedback is used as Gm-stage (Figure 15). For a fair comparison, the same Gm-stage is used for both the topologies. The specification of the transconductor is given in Table 1. The transistors M1 and M2 have overdrive and threshold voltages of 80?mV and 0.4?V, respectively.
Ideally a transconductor with infinite output impedance is needed. Finite output impedance might limit either the null depth or null bandwidth . If the signal is at DC with a bandwidth of , depending on the requirement of attenuation of the aliasing signal, the value of is chosen.
The Gain, Linearity and NF of the filter are mainly determined by the transconductor. In order to arrive at the required value of these parameters for the filter, various factors need to be considered. Some of them are(1)SNR requirement of the receiver for each standard under consideration,(2)Linearity Requirement of the receiver,(3)Gain, Noise Figure and Linearity Allocation to LNA and Mixer,(4)Blocker’s profile.
The aim is to show that the proposed filter occupies less area on sampling capacitors when compared to the conventional filter. For a fair comparison in simulations, active integration is not used for proposed topology.
Channel Bandwidth and Blocker’s profile determines the clock frequency. For example, in the analysis carried out in [9, Chapter 3], the initial sampling rates of the two extreme cases of bandwidths, GSM (200?KHz) and 802.11g (20?MHz) are taken to be 72?MHz and 480?MHz, respectively. Here, a sampling frequency of 500?MHz is assumed for comparison of the two topologies.
PAC analysis of Spectre is used to find the transfer function of the discrete-time filters. In discrete-time filters, the output is valid only at one instant of time every (here 4?ns). For the remaining duration, the output is some random value. If PAC analysis is used directly at the output node to find the transfer function, the response obtained would not be accurate . Reference  suggests sampling the output at the required instant and holding it for using ideal analog blocks in Spectre. This is a useful simulation technique for switched capacitor circuits where the frequency of interest, . In charge sampling circuits, in order to find the null performance, the frequency of interest also includes and so on. As suggestion in , if the output is sampled and held for 4?ns, then it is equivalent to multiplying the response of the filter with a filter having null at 250?MHz, which is the frequency where null of the discrete time filter occur. The two nulls get mixed up and cannot be differentiated. The solution is to sample the output at the required instant every 4?ns using ideal switches, discharge the output immediately (say, after 10?ps) and find PAC at this node. This is equivalent to multiplying the output with a having null at 100?GHz (1/10?ps) and the response of the is almost a straight line in the frequency of interest (0–250?MHz). The simulation setup is shown in Figure 16.
Table 2 shows the summary of results. The filter responses are very nearly identical, with some small degradation in the null attenuation at 20?MHz.
A novel technique to implement a sinc22 filter has been proposed. Both the conventional and proposed filters have been simulated in 45?nm technology and the results are compared. The results show that the proposed filter gives the same performance as the conventional topology with 25% area savings on sampling capacitors, which dominates the area occupied by the filter. The proposed topology can also be extended to achieve function with higher downsampling factor. The higher the downsampling factor, the greater is the area savings compared to conventional filter. The proposed filter topology has an additional benefit; it allows charging and reading the sampling capacitor in closed loop with an OTA. In a software defined radio, when linearity and area are of main concern, the usefulness of the proposed filter is evident.
The authors acknowledge the contributions of the students, faculty, and sponsors of the Analog and Mixed-Signal Center at the Texas A&M University. This research project was partially funded under the Army Research Laboratory Cooperative Agreement no. W911NF-08-2-0047.
- J. Mitola, “The software radio architecture,” IEEE Communications Magazine, vol. 33, no. 5, pp. 26–38, 1995.
- R. Bagheri, A. Mirzaei, S. Chehrazi et al., “An 800-MHz-6-GHz software-defined wireless receiver in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2860–2875, 2006.
- A. Yoshizawa and S. Lida, “A gain-boosted discrete-time charge-domain FIR LPF with double-complementary MOS parametric amplifiers,” in Proceedings of IEEE International Conference on Solid-State Circuits (ISSCC '08), vol. 51, pp. 68–69, San Francisco, Calif, USA, February 2008.
- R. B. Staszewski, K. Muhammad, D. Leipold et al., “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2278–2291, 2004.
- P. K. Prakasam, M. Kulkarni, X. Chen, S. Hoyos, and B. M. Sadler, “Emerging technologies in software defined receivers,” in Proceedings of IEEE Radio and Wireless Symposium (RWS '08), pp. 719–722, Orlando, Fla, USA, January 2008.
- G. Xu and J. Yuan, “Performance analysis of general charge sampling,” IEEE Transactions on Circuits and Systems II, vol. 52, no. 2, pp. 107–111, 2005.
- C. A. Laber and P. R. Gray, “20-MHz sixth-order BiCMOS parasitic-insensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels,” IEEE Journal of Solid-State Circuits, vol. 28, no. 4, pp. 462–470, 1993.
- S. Karvonen, T. A. D. Riley, and J. Kostamovaara, “A CMOS quadrature charge-domain sampling circuit with 66-dB SFDR up to 100 MHz,” IEEE Transactions on Circuits and Systems I, vol. 52, no. 2, pp. 292–304, 2005.
- R. Bagheri, A 800-MHz to 6-GHz CMOS software-defined-radio receiver for mobile terminals, Ph.D. dissertation, UCLA, 2007.
- K. Kundert, “Simulating switched-capacitor filters with spectreRF,” http://www.designers-guide.org/Analysis/sc-filters.pdf.
Copyright © 2009 Karthik Raviprakash et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.