Design and Realization of GaAs Digital Circuit for Mixed Signal MMIC Implementation in AESA Applications

Table 2

Comparison among GaAs logic families.

Logic family	Implemented devices	Minimum DC bias needed	Area per power (FoM)	Output buffer stage
BFL [11]	Depletion FETs diodes	2	48	NO
SDFL [12]	Depletion FETs diodes	2	33	NO
CCFL [13]	Depletion FETs diodes	1	21	YES
SCFL [15]	Enhancement FETs diodes	4	60	SI
FFL [16]	Enhancement FETs	1	38	YES
PCFL [17]	Enhancement FETs	1	12	NO
DCFL [18, 19]	E/D FETs	1	12	NO
SBFL [18, 19]	E/D FETs	1	20	YES
F^2L [20]	E/D FETs Diodes	1	50	YES