Table of Contents
International Journal of Microwave Science and Technology
Volume 2013, Article ID 584341, 11 pages
Research Article

An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90nm CMOS

Solutions Research Laboratory, Tokyo Institute of Technology, 4259-S2-14 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan

Received 1 December 2012; Accepted 21 January 2013

Academic Editor: Leonid Belostotski

Copyright © 2013 Sang-yeop Lee et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11 mm2) by adopting 90 nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).