Research Article
Joint Scheme for Physical Layer Error Correction and Security
Table 2
Result of FPGA implementation.
| Parameters | nonpipelined ECBC | Pipelined ECBC | Non-ECBC method |
| Bels | 3328 | 3912 | 28178 | Maximum frequency (MHz) | 130 | 105.7 | 131 | Total flip flop and latches | 1691 | 2058 | 33794 |
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