Table of Contents
ISRN Bioinformatics
Volume 2012, Article ID 195658, 11 pages
http://dx.doi.org/10.5402/2012/195658
Research Article

A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm

1Electrical Engineering and Computer Science Department, The University of Toledo, MS.308, 2801 W. Bancroft Street, Toledo, OH 43607, USA
2Department of Engineering Technology, The University of Toledo, MS.402, 2801 W. Bancroft Street, Toledo, OH 43606, USA

Received 23 May 2012; Accepted 25 July 2012

Academic Editors: F. Couto, B. Haubold, and J. T. L. Wang

Copyright © 2012 Xinyu Guo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Xinyu Guo, Hong Wang, and Vijay Devabhaktuni, “A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm,” ISRN Bioinformatics, vol. 2012, Article ID 195658, 11 pages, 2012. https://doi.org/10.5402/2012/195658.