Research Article
Design of High-Speed Adders for Efficient Digital Design Blocks
Table 1
Delay, power and area consumed for different adders: a comparision.
| Adder | Number of bits | CMOS logic | Transmission gate logic | Area (no of transistors) | Power in W | Delay in sec | Area (no of transistors) | Power in W | Delay in sec |
| Kogge-Stone | 8 | 486 | 4.13 m | | 432 | 1.8799 m | | 16 | 1140 | 7.694 m | | 1056 | 5.2718 m | | 32 | 2658 | 13.648 m | | 2345 | 10.314 m | |
| Sklansky | 8 | 415 | 17.88 m | | 323 | 8.92 m | | 16 | 1047 | 36.34 m | | 763 | 18.73 m | | 32 | 2199 | 65.13 m | | 1659 | 40.2 m | |
| Brent-Kung | 8 | 598 | 0.18 | | 470 | 0.13 | | 16 | 1268 | 0.4 | | 1012 | 0.3 | | 32 | 2494 | 12.5 | | 1982 | 0.614 | |
| Han-Carlson | 8 | 440 | 10.81 m | | 312 | 1.9178 m | | 16 | 992 | 13.54 m | | 736 | 6.411 m | | 32 | 2208 | 13.99 m | | 1696 | 9.825 m | |
| Ling | 8 | 742 | 0.313 | | 530 | 0.139 | | 16 | 1655 | 0.6 | | 1250 | 0.3104 | | 32 | 3382 | 13.3 m | | 2690 | 0.4105 | |
|
|