Table of Contents
ISRN Electronics
Volume 2012, Article ID 473257, 7 pages
Research Article

MOS Current Mode Logic with Capacitive Coupling

1Department of Electronics and Communication Engineering, Delhi Technological University, Delhi-110042, India
2Department of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, New Delhi-110078, India

Received 31 August 2012; Accepted 19 September 2012

Academic Editors: D. Al-Khalili, G. Maruccio, and Z.-M. Tsai

Copyright © 2012 Kirti Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18 μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application.