Table of Contents
ISRN Materials Science
Volume 2012, Article ID 543790, 16 pages
http://dx.doi.org/10.5402/2012/543790
Research Article

Barrier Evaluation by Linearly Increasing Voltage Technique Applied to Si Solar Cells and Irradiated Pin Diodes

Institute of Applied Research, Vilnius University, Sauletekio Avenue 9-III, 10222 Vilnius, Lithuania

Received 8 August 2011; Accepted 19 September 2011

Academic Editors: A. O. Neto and H. Saxén

Copyright © 2012 E. Gaubas et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

E. Gaubas, T. Ceponis, V. Kalendra, J. Kusakovskij, and A. Uleckas, “Barrier Evaluation by Linearly Increasing Voltage Technique Applied to Si Solar Cells and Irradiated Pin Diodes,” ISRN Materials Science, vol. 2012, Article ID 543790, 16 pages, 2012. https://doi.org/10.5402/2012/543790.