Barrier Evaluation by Linearly Increasing Voltage Technique Applied to Si Solar Cells and Irradiated Pin Diodes

<table>Profiles of the BELIV current amplitude in the solar-cell structure containing different (metallization/<svg height="12.4875" id="M390" style="vertical-align:-0.10033pt" version="1.1" viewbox="0 0 16.012501 12.4875" width="16.012501" xmlns="http://www.w3.org/2000/svg">
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</svg>) thickness and area of electrode. The shape of registered current transients within respective depth is shown in the insets.</table>

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fig13

Figure 13

Figure 13: Barrier Evaluation by Linearly Increasing Voltage Technique Applied to Si Solar Cells and Irradiated Pin Diodes 