Figure 7: A nanomagnetic realization of a NAND gate with fan-in and fan-out. The four magnets within the shaded region constitute the basic NAND gate and the remaining eight magnets are used for fan-in and fan-out. Upspin represents logic bit 1 and downspin logic bit 0. In a linear array, if the line joining the centers of the magnets is parallel to the in-plane hard axis, then dipole interaction between the magnets ensures that the ordering is antiferromagnetic, whereas if that line is parallel to the easy axis, then the ordering is ferromagnetic. Note that very specific distances have to be maintained between the magnets and that the arrangement here is different from that in SSL. This figure is adapted from [86] with permission from the Institute of Physics. The magnets are clocked with a 4-phase sinusoidal clock in order to propagate bits unidirectionally from the input to the output port. Each group of magnets labeled I, II, III, and IV is clocked with one phase and the clock phases are shifted from each other by 90°.