Table of Contents
ISRN Electronics
Volume 2012 (2012), Article ID 891480, 7 pages
http://dx.doi.org/10.5402/2012/891480
Research Article

Fabrication of Self-Aligned Graphene FETs with Low Fringing Capacitance and Series Resistance

1Department of Electrical Engineering, Henry Samueli School of Engineering and Applied Science, University of California, Los Angeles, Los Angeles, CA 90095-7065, USA
2Department of Materials Science and Engineering, Henry Samueli School of Engineering and Applied Science, University of California, Los Angeles, Los Angeles, CA 90095-7065, USA

Received 23 July 2012; Accepted 9 August 2012

Academic Editors: L. Belostotski, J. Solsona, and E. Tlelo-Cuautle

Copyright © 2012 Yanjie Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Graphene FETs with top-gate and buried-gate structure has been studied. The buried-gate structure shows less fringing capacitance and more reliable contacts. High-performance graphene transistors with self-aligned buried gates have been fabricated. The graphene transistor shows field-effect mobility of over 6,000 cm2/V · s according to the transconductance measurement. The contact resistance and intrinsic mobility have been extracted from both curve fitting and transfer length measurement, and the two results agree well. This result paves the way of high-quality graphene transistor technology for the RF application.