Table of Contents
ISRN Electronics
Volume 2012 (2012), Article ID 916259, 9 pages
Research Article

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

Department of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331, USA

Received 25 January 2012; Accepted 26 February 2012

Academic Editor: S. Nikolaidis

Copyright © 2012 Jacob Postman and Patrick Chiang. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Scaling CMOS process technology continues to enable increased levels of system integration, leading to on-chip communication demands beyond what traditional digital signaling techniques can efficiently provide with sufficient reliability. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and provide a review of interconnect reliability considerations. Finally, we provide a case study to evaluate the efficiency of error correcting codes on a state-of-the-art energy-efficient low-swing interconnect.