A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

Figure 1

Minimum reduction in voltage swing that must be achievable at the same or better BER in order to break even with non-error corrected interconnect efficiencies as calculated using (4) and assuming values of 𝐶_wire=260 fF for 1 mm differential wires, 𝐸_txrx=5 fJ and 𝐸_ecc as reported in Table 2 with 𝑉_DD=500 mV.