Table of Contents
ISRN Electronics
Volume 2013, Article ID 187127, 4 pages
http://dx.doi.org/10.1155/2013/187127
Research Article

Novel Low Complexity Pulse-Triggered Flip-Flop for Wireless Baseband Applications

Department of Information and Communication Engineering, Chaoyang University of Technology, 168 Jifong E. Road, Wufong Township, Taichung County 41349, Taiwan

Received 3 April 2013; Accepted 28 April 2013

Academic Editors: S. Gift and S. Martini

Copyright © 2013 Hung-Chi Chu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. V. Stojanovic and V. G. Oklobdzija, “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,” IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 536–548, 1999. View at Publisher · View at Google Scholar · View at Scopus
  2. H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, “Flow-through latch and edge-triggered flip-flop hybrid elements,” in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC '96), pp. 138–139, February 1996. View at Scopus
  3. F. Klass, C. Amir, A. Das et al., “A new family of semi-dynamic and dynamic flip flops with embedded logic for high-performance processors,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 712–716, 1999. View at Publisher · View at Google Scholar
  4. J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, “Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors,” in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 147–152, Huntington Beach, Calif, USA, August 2001. View at Scopus
  5. B. Kong, S. Kim, and Y. Jun, “Conditional-capture flip-flop for statistical power reduction,” IEEE Journal of Solid-State Circuits, vol. 36, no. 8, pp. 1263–1271, 2001. View at Publisher · View at Google Scholar
  6. Y. H. Shu, S. Tenqchen, M. C. Sun, and W. S. Feng, “XNOR-based double-edge-triggered flip-flop for two-phase pipelines,” IEEE Transactions on Circuits and Systems II, vol. 53, no. 2, pp. 138–142, 2006. View at Publisher · View at Google Scholar · View at Scopus
  7. C. Villa, D. Vimercati, S. Schippers et al., “A 65 nm 1 Gb 2b/Cell NOR flash with 2.25 MB/s program throughput and 400 MB/s DDR interface,” IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 132–140, 2008. View at Google Scholar
  8. J. Bauer, S. M. Trimberger, and S. P. Young, “FPGA memory element programmably triggered on both edges,” U.S. Patent 6072348, 2000.
  9. Y. T. Hwang, J. F. Lin, and M. H. Sheu, “Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 361–366, 2012. View at Publisher · View at Google Scholar · View at Scopus