A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell

Table 1

Simulation results at 0.9 V power supply and 200 MHz clock frequency.

Design	Delay (psec)	Power (𝜇W)	PDP (aJ)
Proposed	12.980	0.56878	7.3827
Multi-output Bridge	43.767	0.52364	22.918
Multi-output CAP	121.02	0.82386	99.706
Zipper	19.289	0.48637	9.7060
Majority-based	13.695	1.28330	17.574
SD-10T	40.052	0.50209	20.109
DDCVS	14.724	0.52492	7.7289