A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell

Table 2

Simulation results at 0.9 V power supply and 2 GHz clock frequency.

Design	Delay (psec)	Power (𝜇W)	PDP (aJ)
Proposed	15.337	5.7311	87.897
Multi-output Bridge	43.961	5.2829	232.24
Multi-output CAP	130.18	7.2148	939.23
Zipper	19.705	4.9108	96.766
Majority-based	15.126	6.5500	99.078
SD-10T	36.835	4.2811	157.69
DDCVS	16.007	5.1890	83.061