#### Abstract

The paper presents a new quadrature oscillator of third order which can provide four quadrature current outputs and two quadrature voltage outputs. The new circuit employs three differential voltage current conveyors and six passive components, most of which are in grounded form. Circuit operation at high frequencies is verified along with nonideality and parasitic study. The circuit enhancement for generation of four phase clock waveforms is also given. The proposed circuit is a novel addition to the oscillator family.

#### 1. Introduction

Realization of quadrature oscillators using current mode active building blocks has received continuous attention ever since the advent of current conveyors. The literature has thus witnessed voluminous works which may run into an equally voluminous bibliography, which is beyond the scope of the present discussion and hence limited to some selected works of the last few decades [1–10]. Differential voltage current conveyor became popular in the late 1990s and continued to find applications in realizing oscillators till recently [11–17]. Besides the realization of multiphase oscillators, third-order quadrature oscillators found special attention owing to their low-distortion output generation capability [18–24]. As a result, numerous high performance oscillator circuits continue to find most recent space in the literature [25–29].

In this paper a new third-order quadrature oscillator based on DVCCs is proposed. The proposed circuit requires three DVCCs, three grounded capacitors, and three resistors, of which two are grounded. The circuit generates four quadrature current outputs at high impedance nodes and two quadrature voltage outputs. The circuit usability at high frequencies with low THD is demonstrated. The nonideal analysis as well as parasitic analysis is included to study the real world performance of the proposed circuit. The new proposal further enriches the subject area. Section 2 presents the actual circuit description. Section 3 is devoted to the nonideal analysis. Parasitics considerations are given in Section 4. Simulation results are given in Section 5. Application of the proposed circuit is further explored in Section 6. Lastly, Section 7 presents conclusion of the paper.

#### 2. Proposed Circuit

##### 2.1. Circuits’ Description

The symbol and CMOS implementation of differential voltage current conveyor (DVCC) are shown in Figure 1. DVCC is a five-port building block and is characterized by the following port relationship: In a DVCC, terminals , exhibit infinite input impedance. Thus no current flows in terminal , . The terminal exhibits zero input impedance. The and terminals exhibit high output impedance. The proposed circuit of third order quadrature oscillator is shown in Figure 2. It is composed of three DVCCs, three grounded capacitors, and three resistors.

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The characteristic equation of the circuit can be expressed as Replacing with and equating real and imaginary terms, the above equation yields the frequency of oscillation (FO) and condition of oscillation (CO) as Assuming equal value resistors () and capacitors (), the expressions of (3) and (4) are simplified to The various voltage and current outputs depicted in Figure 3 are related as It is evident from (6) that two quadrature voltages in the forms of and with a phase shift of 90° are obtained. It is quite worth noting that the voltage outputs unlike the available current outputs do not appear at appropriate (low) impedance level. The four current outputs are available at desired high impedance level and also exhibit a quadrature relationship. Four quadrature current outputs in the forms of , , and with a progressive phase shift of 90° are obtained. The various outputs generated have equal amplitudes. The sensitivity figures of FO with respect to passive components are low and given in Equation (7) shows that the sensitivity figures for the proposed circuit are found to be less than unity, which implies good sensitivity performance.

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#### 3. Nonideal Analysis

Taking the nonidealities of the DVCC into account, the relationship between the terminal voltages and currents of the DVCC can be rewritten as: Here, and are the voltage transfer gains from and terminals, respectively, to the terminal. And is the current transfer gain from terminal to and terminals. The above transfer gains deviate unity by the voltage and current transfer errors, which are quite small and technology dependent. Moreover, the transfer gains, instead of being real, are actually frequency dependent with an upper bound on the usable frequency.

The third-order quadrature oscillator of Figure 2 is reanalyzed using (8) so as to obtain the characteristic equation as:
The modified frequency of oscillation and condition of oscillation are
Here, , are the voltage transfer gains from , terminals, respectively to the terminal of DVCC_{1}, and is the voltage transfer gain from terminal to the terminal of DVCC_{3}. is the current transfer gain from the terminal to terminal of DVCC_{1}, is the current transfer gain from the terminal to terminal of DVCC_{2} and is the current transfer gain from the terminal to terminal of DVCC_{3}. It is to be noted that (10) reduces to (3) and (11) reduces to (4) for the ideal value of the transfer gains, which is equal to unity. The active and passive sensitivities are given in
The sensitivities of active and passive components are within unity in magnitude. Thus, the new circuit of third-order quadrature oscillator enjoys attractive active and passive sensitivity performances. It can be further observed from (10) and (11) that the non-idealities slightly change the frequency of oscillation and condition of oscillation.

#### 4. Parasitic Considerations

The various parasitics involved with a typical current conveyor [30] are well known. Like the second-generation current conveyor (CCII), the DVCC has a small parasitic resistance at port , high input impedance () at port , and high input impedance () at terminal. The parasitic model of DVCC is shown in Figure 4. As the terminal of the DVCC_{1}, DVCC_{2}, and DVCC_{3} is connected to a resistor, the parasitic resistance at the terminal of the DVCC () can be absorbed as a part of the main resistance. As the value of , , and is much smaller than that of, the external resistors, frequency of oscillation of the proposed circuit of third-order quadrature oscillator will be slightly affected. The effects of the capacitors at ports and of the DVCC are also negligible because these capacitors are quite small (and process dependent) as compared to the external capacitors. However, the proposed circuit of quadrature oscillator is reanalyzed taking into account the above parasitic effects. A reanalysis of the proposed circuit of quadrature oscillator yields
where
where , , and , , , and , , .

From (13) it is clear that the parasitic resistances and capacitances appear in shunt with external capacitors, which are connected at terminals, thus ensuring a possibility of predistorting the designed values. Therefore it is to be concluded that the circuits are not adversely affected by the parasitic resistances and capacitances. Moreover, from (13), it can be further observed that the parasitic resistances/capacitances merge with the external value. Such a merge does cause slight deviation in circuit’s parameters, which can be eliminated by predistorting the element values to be used in the circuit.

#### 5. Simulation Results

The proposed third-order quadrature oscillator was next simulated using PSPICE, an industry standard tool for evaluating the performance of circuits. The CMOS implementation of DVCC in Figure 1(b) was used with 0.5 *μ*m CMOS parameters and aspect ratios as listed in Tables 1 and 2, respectively, and the supply voltages were V. The biasing voltage was taken as −1.4 V. The circuit was designed using equal capacitors and resistors of values pF and, kΩ. The theoretical FO using this design was 7.96 MHz. The simulated FO was found to be 7.94 MHz, which is very close to the theoretical value and only 0.25% in error. The results for the four current outputs and two voltage outputs are shown in Figures 5 and 7 respectively. The Fourier spectrum of the outputs of Figures 5 and 7, are shown in Figures 6 and 8, respectively. The THD at various outputs is listed in Table 3. A low THD along with good accuracy of the FO is a justifying feature for the third-order oscillator. To further support the circuit’s practical utility, (for ) was varied so as to vary the FO. The FO tuning through is shown in Figure 9. The FO is found to vary from 3.18 MHz to 10.62 MHz for variation of from 10 KΩ to 3 KΩ, respectively. Both theoretical and simulated FO are found to be closely matched; the discrepancy in simulated frequency being the result of various nonidealities and parasitics as discussed in Sections 3 and 4.

#### 6. Circuit Enhancement

Next, a new application of the proposed third-order quadrature oscillator in clock generation is given. A four phase clock (, , and ) along with two sine waveforms ( and ) is generated by using the proposed circuit of oscillator (Figure 2). The block diagram representation is shown in Figure 10. For generation of four phase clocks, four voltage outputs are taken instead of four current outputs (as shown in Figure 2) at the terminals of DVCC_{2} and DVCC_{3}. The four phase clock voltage outputs are at a progressive phase shift of 90°. Note that the terminals exhibit a high output resistance, sufficient to saturate the DVCCs. The output levels depend on the supply voltage ( and ). No additional resistors are being used, and thus the new scheme is compatible with monolithic implementation. The results of the four phase clock are shown in Figure 11 and very well justify this new application.

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#### 7. Conclusion

A new third-order quadrature oscillator circuit based on three DVCCs as active element, three grounded capacitors, and three resistors is presented. The circuit provides both quadrature voltage and current outputs. The circuit exhibits good high frequency performance. The enhancement of the proposed circuit as sine/clock generator is further given. PSPICE simulations using 0.5 *μ*m CMOS parameters support the validity and practical utility of the proposed circuit.

#### Acknowledgment

The authors thank Academic Editors for recommending this paper. The paper was submitted at the time when article processing charges for the Journal were waived off.