Table of Contents
ISRN Nanotechnology
Volume 2013, Article ID 587436, 7 pages
Research Article

Design of a Single-Electron Memory Operating at Room Temperature

Laboratoire de Microélectronique et Instrumentation (UR/03/13-04), Faculté des Sciences de Monastir, Avenue de l’Environnement, 5019 Monastir, Tunisia

Received 16 June 2013; Accepted 15 July 2013

Academic Editors: G. Alfieri and K. H. Park

Copyright © 2013 Amine Touati et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Single-electronic transistors (SETs) are considered as the attractive component for the next generation of transistors due to their ultrasmall size and low power consumption. Because SETs with single island cannot work at high temperature normally, more researchers begin to carry out research on the SETs with N-dimension multi-islands. In this paper, we introduce a new architecture of single-electron memory; ideally the memory should operate in combination of SETs with a nanowire of two-dimensional regular array of multiple tunnel junctions (MTJs). This structure is analyzed and studied with Monte Carlo simulator, SIMON. The Coulomb blockade effect and thermionic effect play an important role in carrier conduction in the system at room temperature. Nanowire MTJs are used as an electrometer to sense the memory-node charge. The well-defined parameter in tunnel junction circuits helps to obtain the charging of single electrons in these circuits at room temperature.