Low Power Decoding of LDPC Codes

Table 4

ATBF decoder implementation results.

Decoding algorithm	ATBF
CMOS fabrication process	90 nm, 5 M
Supply voltage	0.9 V
Clock speed	250 MHz
Parallelism	Fully parallel
Message bits	4
Logic utilisation	63.75%
Total chip area	0.729 mm^2
Throughput (at 10 iterations)	25.2 Gb/s
Throughput per area (Gb/s/mm^2)	34.6
Power consumption	33.14 mW
Energy/bit	1.3 pJ/bit