Table of Contents
ISRN Electronics
Volume 2013, Article ID 850267, 9 pages
Research Article

Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA

1Department of Computer Science and Engineering, National Institute of Technology, Durgapur 713209, India
2Department of Computer Science and Technology, Bengal Engineering and Science University, Shibpur 711103, India

Received 28 April 2013; Accepted 26 May 2013

Academic Editors: D. Rossi and P. Wachulak

Copyright © 2013 Bibhash Sen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.