International Scholarly Research Notices

International Scholarly Research Notices / 2014 / Article

Research Article | Open Access

Volume 2014 |Article ID 391240 |

Grzegorz Szczepkowski, Ronan Farrell, "Study of Linearity and Power Consumption Requirements of CMOS Low Noise Amplifiers in Context of LTE Systems and Beyond", International Scholarly Research Notices, vol. 2014, Article ID 391240, 11 pages, 2014.

Study of Linearity and Power Consumption Requirements of CMOS Low Noise Amplifiers in Context of LTE Systems and Beyond

Academic Editor: G. Snider
Received05 Dec 2013
Accepted22 Jan 2014
Published04 Mar 2014


This paper presents a study of linearity in wideband CMOS low noise amplifiers (LNA) and its relationship to power consumption in context of Long Term Evolution (LTE) systems and its future developments. Using proposed figure of merit (FoM) to compare 35 state-of-the-art LNA circuits published over the last decade, the paper explores a dependence between amplifier performance (i.e., combined linearity, noise figure, and gain) and power consumption. In order to satisfy stringent linearity specifications for LTE standard (and its likely successors), the paper predicts that LNA FoM increase in the range of +0.2 dB/mW is expected and will inevitably translate into a significant increase in power consumption—a critical budget planning aspect for handheld devices, active antenna arrays, and base stations operating in small cells.

1. Introduction

Long Term Evolution (LTE) is a next generation communication standard developed by 3rd Generation Partnership Project (3GPP) [1], allowing a high data rate transmission over radio interface. It represents a natural progression from voice transmission systems as GSM through UMTS (with increased spectral efficiency for data transmission) to data transmission scheme, where the majority of system throughput is used for high quality audiovisual streaming, internet access, file sharing, and gaming, with peak downlink bandwidths in excess of 100 Mbps [2].

Such a dramatic increase in data throughput corresponds to proportional increase in either a bandwidth (BW) or signal to noise ratio (SNR) or both at the same time. Both quantities cannot be made arbitrary high. SNR is a function of maximum transmitted power allowed for the system, distance to the receiver, and modulation scheme, and these parameters are usually optimised for the transmission. BW is controlled by the availability of a radio spectrum allocated for the system and, to certain extent, more bandwidth can be assigned to increase channel capacity if needed (providing that there is enough amount of unoccupied bandwidth left). Nowadays, the number of various wideband radio systems coexisting with LTE is significant and as a result, the radio spectrum has become relatively congested. For example, 3GPP specifies LTE frequency separation between frequency-division duplex (FDD) uplink and in the range of 45–400 MHz or even smaller distance (for time-division duplex (TDD) transmission bands) [1].

From a radio receiver perspective, in order to prevent unwanted signals from reaching processing stages, small frequency separation between bands imposes high selectivity (or signal rejection). Historically, the most practical one has been the use of high quality factor preselection filters (duplexers in transceivers) after the antenna; however in context of the wideband operation of LTE system, this approach becomes less practical. Since LTE transceivers operate in UHF band, 0.7–2.7 GHz (note that the range is not continuous), it is impossible to design a single RF preselection filter that is simultaneously wideband and has high roll-off characteristics and its centre frequency can be tuned to any band of interest.

When high performance wideband filter is not available, together with a wanted signal, radio receiver detects and tries to process many unwanted components of the spectrum, in most cases having an average power much larger than that of the signal of interest. This would not present a serious problem if the receiver was a completely a linear system (also not limited by maximum power supply voltages and currents), having ability to process signal of any strength with constant performance. In practice, however, the receiver subcircuits consist of number of transistors and the relationship between input and output is nonlinear.

As a result, all of the unwanted signals in the receiver cross-modulate into wanted frequencies, dramatically reducing the effective SNR and transmission throughput. Nonlinearities also reduce gain of a wanted signal through two mechanisms known as compression and blocking, reducing SNR of received signal even further. Thus, in order to mitigate problem of the destructive interference, special care has to be taken to design a receiver system with high linearity, especially where a preselection filtering is far from ideal.

This paper addresses the question of how high linearity levels of LNA have to be to satisfy LTE requirements for given SNR and what is a possible power penalty for achieving this goal, providing a vital information on how much power has to be budgeted for an RF receiver front-end design. Linearity and power relationship is important not only for battery operating systems as handsets but also for base stations in femto-, pico-, and metro-cells, operating with reduced power budget and multiple receivers. To our knowledge, a presented study on LTE linearity performance in relation to various CMOS LNA designs and its power budgets has not been conducted before.

This paper is organised as follows. Section 2 introduces fundamental aspects of amplifier linearity together with the corresponding metrics. Section 3 describes three basic linearization techniques used in many state-of-the-art LNA designs, with special emphasis on power consumption. Using system specification from 3GPP, the linearity requirements for LTE receiver are derived in Section 4, whereas Section 5 discusses their impact on both standalone LNA circuit and RF front-end design. Finally, Section 6 introduces a figure of merit function that enables fair comparison between different published state-of-the-art CMOS LNA circuits. Also we formulate a prediction of relative power supply levels necessary for future designs of LTE-compatible and beyond for integrated RF LNAs.

2. Amplifier Linearity Analysis

2.1. Taylor Series Description of Soft Nonlinearity

Circuits utilising transistors are characterised by a nonlinear relationship between their inputs and outputs. The main source of this behaviour comes from the features of semiconductor materials, where electrical properties are strongly dependant on electrical potential energy. In general, transistors are used as switches and/or amplifiers (or more precisely transducers providing some form of proportional transformation between voltages and currents). When used as an amplifier, MOS transistor can be characterised by a soft nonlinearity [3]; that is, one can find a polynomial of a finite order, sufficiently describing the nonlinearity within a limited range of input signal levels around certain bias point. In the simplest of cases, Taylor series defines such a polynomial; however when reactive components (e.g., transistor capacitances) become important, Volterra series approach is used instead [3]. As an example, consider a simple low voltage LNA transconductance amplifier in common source (CS) configuration, biased using a NMOS current mirror, depicted in Figure 1.

Inductors and have high impedance at frequency of interest; capacitors provide AC coupling to a following stage connected to the LNA. Please note that for the following linearity analysis we assume that impedance matching, noise figure, and bandwidth are not critical. In practice all of these constraints have to be optimised simultaneously, which leads to a more complex relationship between parameters and circuit architecture. The output AC current of flowing through can be described by the following polynomial: where is th coefficient of the polynomial, defined as That is, represents th derivative of in respect to the input voltage, for the device biased at certain DC point. Note that when the quiescent point of a soft nonlinearity changes, the coefficients described by (2) have to be recalculated. Typically, the infinite series given by (1) is well approximated by the first 3 to 5 elements, as is inversely proportional to factorial of .

Polynomial description reveals the effects of intermodulation, gain compression, and blocking taking place in a nonlinear amplifier. Using trigonometric identities and assuming that input voltage consists of two signals operating at different frequencies, we can show (for nonzero and coefficients) The output current (1) consists of many different harmonic components: these given by (4) are the second order intermodulation products, IM2, whereas (5) and (6) are known as the third order intermodulation products, IM3. Note that the magnitudes of IM2 and IM3 are proportional to and , and they increase much faster than the first order output terms given by Equations (7) and (8) show that the transconductor output at and depends on amplitudes of both signals. Interestingly, for , the output current is reduced by large amplitudes of wanted input signal (gain compression) and the strong interference (known as blocking, , and terms, resp.).

Formulas (4)–(8) are used as basic metrics for linearity analysis, known as input intercept points (IIP) [4, 5]. As mentioned previously, IM products amplitude increases faster than the amplitude of fundamental signal; therefore it is possible to find theoretical input amplitudes and for which the resulting IM products equalize with the fundamental. The second order (IIP2) and third order (IIP3) intercept points are, respectively, defined as [4, 5] Typically, values for IIP2 and IIP3 are much larger than the maximum voltages and currents allowed in the circuit. The intercept points are approximated by finding crossover points of the tangent lines from measurements of IM2, IM3, and fundamental response. As far as a linearity of LNA is concerned, the higher the IIP2 and IIP3, the better the performance of the amplifier. Note that RF literature and vendor datasheets typically express both intercept points in terms of power referred to 50 Ω. And this standard notation is followed in this paper.

2.2. IIP2 and IIP3 Analysis Example

As an example, consider large signal model of an UMC 130 nm NMOS RF transistor (μm, μm, , , and  V) operating in the LNA circuit from Figure 1. The polynomial coefficients (2) were obtained using Eldo RF simulator. Using (9) we can calculate IIP2 and IIP3 as function of gate bias voltage for the amplifier in question. The results are depicted in Figure 2.

The presented curves show that there are three possible bias points for improved linearity, where IIP2 and IIP3 are at their respective maximums:(i)mV, μA, mA/V, mW,   dBm, and  dBm.At this point IM3 products are minimised as well as a power consumption. Transistor is biased, where , resulting in high IIP3. IM2 products are not minimised, but they are usually not a limiting factor for a linearity performance of the receiver when originated from LNA [4, 5]. However, at this bias point, small value translates into reduced gain and from a noise perspective; this has a negative impact on system SNR. Since unity gain frequency of the transistor is proportional to , the maximum operation frequency of the circuit is limited.(ii)mV, mA, mA/V, mW,  dBm, and  dBm.At this point IM2 products are minimised; IM3 products are relatively small as well. The transconductance is at its maximum, 2.6 times larger than in the previous case, improving both gain and . The cost however is 21 times more power dissipated by the transistor than before.(iii)mV, mA, mA/V, mW,   dBm, and  dBm.Depending on the system requirements (discussed in detail later in this paper), this point may represent a design trade-off between power consumption and linearity, delivering 90% of maximum gain with more than a 60% of power reduction in comparison to the previous case.

As mentioned before, in practice the design of LNA has to involve a simultaneous optimisation of noise, impedance matching, gain, stability, and linearity (as all of these cannot be maximised at the same time); however the presented methodology can be used as a starting point for a linear LNA design with a limited power budget.

3. Linearization Techniques

It is natural to expect that the relationship between power consumption and linearity of an LNA is much more complex than highlighted in the previous section (in other words it is not only the function of transistor bias point). In the context of this work it is important to shed more light on how linearity of an amplifier can be improved by various circuit techniques that among other design constraints significantly affect the power consumption as well.

3.1. Negative Feedback

Figure 3 depicts well known negative feedback (FB) circuit configuration. FB samples a fraction of the output signal and transmits it back to the amplifier input out of phase. Gray et al. [6] show that effects of soft nonlinearity can be improved because both gain and its sensitivity on input signal are chiefly controlled by a transfer function of feedback loop block . If can be made linear, this translates directly to improved linearity of the whole closed loop system.

Zhang and Sánchez-Sinencio [7] show that if amplifier gain is equal to , IIP2 is improved by as much as , whereas increase in IIP3 is proportional to but only for . When the second order polynomial coefficient is finite, resulting IM2 products are fed back to an amplifier and intermodulate into IM3, quickly deteriorating theoretical improvements in IIP3. The main advantage of FB method is the use of passive components that do not consume power (majority of typical designs employs highly linear RLC components as ). The main drawback is strong dependence of circuit linearity on product that is generally known to vary significantly at RF frequencies, especially in wideband applications.

3.2. Feed-Forward and Derivative Superposition

Another approach to improve LNA linearity is a feed-forward (FF) technique, depicted in Figure 4. In this method, input signal is connected to the inputs of nonlinear amplifier and a parallel block , whereas the output signal is a difference of corresponding output signals from each of the blocks. The block scales input signal by the factor of , passes this signal through auxiliary amplifier with the same nonlinearity as the one of the LNA, and then scales the response down by . As a result, after the final addition, IM3 products from both paths are ideally cancelled out [8, 9]. In practice, due to process variations, IM3 cancellation is limited, requires twice the power (due to an auxiliary amplifier), and increases noise. The FF method relies heavily on constant and precise value for which is hard to obtain in practice and input matching may be problematic, especially in wideband applications [7].

One of the modifications of FF approach, known as derivative superposition (DS), uses nonlinearity with 3rd order polynomial of the opposite sign to the one of the LNA; that is [10, 11]. The main advantage of this method is that IM3 products are automatically out of phase, without necessity of using scaling factor as in the standard FF approach. In addition, an auxiliary amplifier operates in weak inversion with minimal impact on the power consumption [10, 11]. The disadvantage is a limited range of relatively low input amplitudes block can operate with [7].

3.3. Postdistortion

Last method, presented in Figure 5, is known as postdistortion (PD) and involves the auxiliary nonlinearity supplied after the LNA [12]. This block is characterised by the same nonlinearity as LNA however with opposite sign, effectively grounding IM products but passing linear response to the output. The most important advantage is that input matching of LNA is not affected as in the case of FF methods mentioned previously. The drawback is increased power consumption as is usually biased in saturation for robust distortion cancellation.

The three fundamental linearization techniques referenced in this work show that in some cases nonlinear behaviour of the amplifier can be improved without power increase (FB), whereas a further suppression of IM products requires more energy. As a result, in practice the prediction of power consumption required for certain linearity is a more complex process. We will focus on this issue towards the end of this paper.

4. LTE Linearity Requirements

4.1. 3GPP LTE Specification and System Parameters

The linearity requirements for LTE are not reported specifically by 3GPP; however after some elaboration they can be derived from the intermodulation specifications 36.101 and 36.104 [1] for both user equipment (UE) and base station (BS) receivers, respectively. In this paper we use the most recent version of aforementioned LTE specification, Revision 11, March 2013, and we limit our calculations to UE, as BS has more scenarios differing in performance (namely, Wide Area, Medium Range, Local Area, and Home). However, the presented formulation can be successfully applied to any type of BS if necessary. In order to represent performance variations in different propagation scenarios, 3GPP considers reference carriers with QPSK, 16QAM, and 64QAM modulations and following bandwidths: 1.4, 3, 5, 10, 15, and 20 MHz. In this work we present calculations for QPSK case for all bandwidths and for a single LTE Band 2 (uplink, UL, centred 1960 at MHz, downlink, DL, at 1880 MHz, 60 MHz bandwidth, 80 MHz separation) [2]. Finally, as mentioned previously, we will focus only on IIP3 as assuming that the second order distortion in LNA is not usually a limiting factor for the linearity of complete receiver.

All system parameters necessary to calculate IIP3 are presented in Table 1.(i) is a minimum average power applied to UE antenna ports (LTE assumes 2 Rx antennae for diversity scheme) to achieve at least 95% of maximum throughput.(ii)Thermal noise floor for given bandwidth at temperature of 290 K.(iii)  Margin is a required increase in minimum average received signal power in the presence of blockers and interferers over nominal value.(iv)3GPP derives intermodulation requirements for two interfering signals; one is a continuous wave (CW); the other one is a modulated carrier with bandwidth ranging in between 1.4 and 5 MHz.

Param.Bandwidth (MHz)

Noise floor (dBm)−113−109−107−104−102−101
Rx Margin (dB)1296679
Int BW (MHz)1.435

4.2. In-Band IIP3 Specification

In-band linearity requirement defines receiver robustness against cross modulation products of other channels of the same band or any CW interferer present within the band of interest. According to 36.101 rev.11 specification, the receiver has to be able to detect a wanted signal in presence of two interferers with average power of −46 dBm each. CW interferer is placed at −BW/ MHz (low side) or BW/ MHz (high side) from the carrier frequency of the band of interest, whereas the modulated interferer is located at twice the frequency of the CW signal. For example, considering high side interferers and BW of a wanted signal of 10 MHz, the CW interferer is located at 12.5 MHz from the carrier, whereas 5 MHz modulated interferer is 25 MHz above the carrier. It is easy to show that one of their IM3 products at is centred around the carrier as well: Assuming that the intermodulation products are allowed to increase noise floor from Table 1 by Rx Margin of 6 dB (assuming channel bandwidth of 10 MHz), resulting in maximum noise floor of −98 dBm. Since thermal noise and IM3 products are not correlated, we can calculate the maximum power of intermodulation components: As the interferer bandwidth is 5 MHz for the considered case, IM3 product occupies exactly half of the signal BW. Thus, (11) has to be corrected by the ratio of two quantities, which now represents an equivalent average IM level for 10 MHz wanted signal [13]: Finally, IIP3 can be estimated taking power of interferers and calculated power of the third order intermodulation product [13]: Table 2 presents the results of in-band IIP3 calculations for all the possible BW values. Note that our calculations are 3-4 dB more stringent to the results of Sesia et al. [13], where the authors used an average implementation margin of 2.5 dB in their calculation but did not provide any explanation behind this choice. Thus, we assumed that in practice more implementation margin may be necessary, for example, due to process variations.

BW (MHz)P IM3 (dBm)In-band IIP3 (dBm)Out-of-band IIP3 (dBm)


4.3. Out-of-Band IIP3 Specification

Due to a limited performance of receiver preselection filters and finite isolation of duplexer in radio transceiver, strong signals from the transmitter side are injected into the receiver and are mixed together with interferers into IM3 products, as presented in Figure 6. This is chiefly a problem for FDD system, where the transmitter and receiver are operating simultaneously. Taking a maximum average power of LTE signal from the transmitter output of +24 dBm, a typical duplexer isolation of 50 dB, and 2 dB losses in the receive path [13], interferer as strong as −28 dBm can reach the receiver. If a strong CW signal falls between Rx and Tx bands (namely, at half the duplex distance) IM3 products will fall into the band of interest. As previously, IIP3 specification is reported directly by 3GPP; however it can be derived from out-of-band blocking requirements [13, 14]. The maximum power of CW interferer depends on its distance from the edge of a wanted band and is, respectively (in reference to the upper limit), −4 dBm from 15 MHz to 60 MHz, −30 dBm from 60 MHz to 85 MHz, and −15 dBm above 85 MHz offset [1]. For Band 2 considered in this paper, the duplex separation is equal to 80 MHz; thus a −44 dBm CW interferer at 40 MHz offset from the received band cross-modulates with the transmitter leakage. As Band 2 has a relatively wide UL and DL bandwidths in relation to the duplex distance (60 MHz versus 80 MHz), the resulting filtering of CW between bands will be limited. As an example consider a commercially available Band 2 duplexer from Avago Tech., ACMD-7410, that provides approximately 4 dB attenuation at CW frequency [15]. Thus, interferer of −48 dBm has to be considered. As both CW and the leakage signal power in relation to the receive band are strong functions of duplexer transfer function, Sesia et al. [13] suggests using an average interference power to calculate IIP3. In the presented example, the average power of the interference from −28 dBm leakage and −48 dBm CW is equal to −31 dBm. Using (13) and assuming allowed power of IM3 products from (11) and (12), the resulting out-of-band IIP3 values are presented in Table 2.

It can be seen that the out-of-band requirement is much more stringent than in the case of in-band calculation (−17 dBm against +5 dBm). In the case of the former, a duplexer specification determines the linear performance of the receiver (this is most likely why 3GPP does not define IIP3). In the case of stronger interferers and limited filtering in wideband applications, this leads to further increase in out-of-band IIP3 levels.

5. Linearity: Amplifier versus LTE Front-End

In order to show how system level linearity translates to IIP requirements of LNA, let us consider a simplified model of cascaded RF heterodyne front-end, depicted in Figure 7. The system consists of an LNA, followed by a mixer and intermediate frequency (IF) amplifier. Each block is described by the power gain as well as IIP3. We assume that all blocks are impedance matched, which in practice is valid only for a limited range of frequencies. For clarity, any interstage filters were omitted, assuming that at frequency of interest they introduce negligible insertion loss and their respective IIP3 levels are relatively high.

Well known approximation of 3 stage cascade from Figure 7 is given by [4, 5] where represents power gain and IIP3 is power referred to a characteristic impedance common for all the blocks. Although simple, (14) allows us to analyse how LNA affects the performance of the cascade. The rule of thumb is that the linearity of the cascade is defined by the last stage (IF amplifier in Figure 3) as its IIP3 is scaled down by the total gain of previous stages. This is generally true assuming that linearity of LNA and mixer are not limiting factors. In practice, however, in order to provide wide bandwidth, constant gain, and low noise figure, linearity of the LNA cannot be designed arbitrarily high. In addition, in order to reduce front-end power consumption and improve noise figure and linearity, a passive mixer with negative conversion gain can be used. Thus, the more detailed analysis is necessary. As an example consider a typical IF amplifier with power gain of 20 dB and IIP3 in the range of 25 to 30 dBm [16]. Assuming a constant gain of the LNA and passive mixer, equal to 15 dB and −6 dB, respectively, we can show that the total IIP3 of the cascade from (14) is strongly dependent on both intercept point levels of LNA and mixer.

Figure 8 depicts the results of total IIP3 calculation as a function of LNA linearity for the parametric sweep of mixer third order intercept point. Dashed line represents a +5 dBm IIP3 target corresponding to LTE out-of-band specification calculated in Section 4.

It can be seen that for low values of LNA  dBm, the amplifier limits the linearity of the cascade. The curves start to diverge strongly where LNA IIP3 reaches 0 dBm. At this point the mixer intercept point is reduced by the LNA gain and becomes the dominant factor. Finally, a highly linear LNA has no effect on the total IIP3 of the cascade, now controlled fully by the intermodulation performance of the mixer. Thus, in order to achieve out-of-band IIP3 performance of the LTE system, it is critical to use both highly linear mixer and LNA combinations. Providing that typical RF passive mixers in discrete implementations achieve IIP3 in the range of 25 to 35 dBm [16], a rough estimation of intercept point for LNA operating in LTE receiver yields +5 dBm. In practice, we should expect limited performance due to impedance mismatches, nonuniform gain changing with frequency, and nonideal duplexer transfer function. It is therefore safe to assume that IIP3 of +10 dBm is more realistic target for LTE wideband low noise amplifier.

6. LNA Power Consumption in Context of LTE

This section presents the results of performance comparison of 35 different CMOS wideband LNA circuits published in recent years (Table 3, on a following page) [1749]. To allow fair comparison, every circuit is characterised by power gain (, dB), noise figure (NF, dB), minimum and maximum frequency of operation ( and resp., MHz), fractional bandwidth (FBW), IIP3 (dBm), and DC power (, mW). Note that some of the published circuits use a voltage gain in place of power gain. In order to follow system level design standards, we translated gain of all LNAs into power domain. It is assumed that the DC power consumption is referred to LNA core, as many of the authors do not report it explicitly. Fractional bandwidth follows a standard RF definition of a ratio of difference between and to the centre frequency between the two. In cases where and NF were varying over the band of interest, the best of the reported values was chosen.












In order to show that the relationship between linearity of RF LNA and DC power is not straightforward, consider the results of IIP3 comparison, depicted in Figure 9. Dots correspond to the third order intercept points from Table 3, whereas the solid line represents a linear trend calculated on the dataset. It can be seen that IIP3 is weakly dependent on power consumption (+0.06 dB/mW). Counterintuitive at first, this behaviour is expected. As indicated previously in Section 2, power increase can help to reduce intermodulation effects in simple LNAs; however it may not necessarily yield the best noise, impedance matching, and stability performance. For example, in comparison with other circuits, two LNAs with the highest linearity have either relatively low fractional bandwidth [27] or high noise figure [38]. Note that among the reported state-of-the-art CMOS LNAs, only the two described topologies meet IIP3 requirement from Section 3.

In order to include effects of gain, noise, and linearity, figure of merit (FoM) function has to be used. Usually the DC power consumption contributes to total FoM; however in order to analyse the performance of LNA as a function of the power, we calculate FoM (without power) in  dBm: Note that all of the elements in (15) contribute equally to the total FoM; thus a high performance LNA is characterised by minimum noise, wide tuning range, high gain, and IIP3, resulting in proportionally high FoM values.

Figure 10 depicts the results of FoM calculation. As before, dots represent the data points from Table 3, whereas solid line is a linear trend. The average FoM is equal to 26.8 dBm, with average power consumption of 18.3 mW. It can be seen that higher FoM requires more DC power, which confirms our assumption that optimised wideband LNA consumes more energy. Note that this relationship is not strong as the slope of a trend line is approximately +0.19 dB/mW. In order to increase FoM of CMOS LNA by 3 dB, a corresponding increase in power of 16 mW is necessary. Assuming IIP3 of +10 dBm as a target for LTE LNA (derived in Section 4), together with an average power gain of 15 dB for RF LNA [16], a fractional tuning range of 120% (0.7–2.7 GHz LTE band), and NF of 5 dB (a fair assumption for total NF of 9 dB for the wideband UE LTE receiver), a target FoM of 41 dBm is obtained.

Therefore, the corresponding FoM increase of +14.2 dB over the average, results in a proportional change in DC power by +75 mW, the expected increase in FoM is equal to +14.2 dB, which corresponds to the required increase in power of +75 mW. Note that four of the reported LNAs [23, 27, 32, 38] meet the FoM requirement; however either a bandwidth is smaller, IIP3 is inadequate, or noise is too high for an LTE system (note that the authors usually present the best performance rather than the average over bandwidth). A validity of the presented discussion can be confirmed by a comparison to the state-of-the-art commercial LNA chip ADL5521 from Analog Devices [16]. Although realised in GaAn pHemt technology (higher and lower noise than CMOS), its performance follows the trend of FoM presented in this paper. The reported parameters are (averaged)  dB,  dB,  dBm, and , and calculated FoM is equal to 57 dBm, that is, +30.2 dB above the CMOS average presented in this paper. According to our prediction the LNA core should consume +159 mW more than the CMOS average, resulting in a total of 177 mW. The reported value for ADL5521 is 300 mW from 5 V supply; however the core power consumption is not disclosed (some of the reported power is used by active replica bias). Thus it can be seen that, in practice, high performance LTE LNAs are power hungry circuits, as shown in this paper.

7. Conclusion

The presented results show that, in general, LNA linearity as a standalone parameter is indirectly dependent on power. In theory, for a certain IIP3 performance, LNA circuit can be designed without the penalty of increase in power, as indicated by Figure 8. However, taking into account the rest of design constraints as noise figure, gain, and bandwidth, more power has to be delivered to the amplifier, and hence, increasing LNA linearity levels will inevitably translate into higher power consumption. This is especially crucial for the wideband systems (LTE and beyond), where inadequate filtering leads to more stringent intermodulation specifications that, in turn, present a significant impact on the power consumption of the whole receiver.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.


This material is based upon works supported by the Science Foundation Ireland under Grant no. 10/CE/I1853. The authors gratefully acknowledge this support.


  1. “3GPP Specifications,” 2013, View at: Google Scholar
  2. H. Holma and A. Toskala, LTE for UMTS: OFDMA and SC-FDMA Based Radio Access, Wiley, Chichester, UK, 2009.
  3. P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits, Kluwer Academic Publisher, Boston, Mass, USA, 1998.
  4. B. Razavi, RF Microelectronics, Prentice Hall, Englewood Cliffs, NJ, USA, 1998.
  5. T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, Cambridge, UK, 2004.
  6. P. R. Gray, P. Hurst, S. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Wiley, New York, NY, USA, 4th edition, 2001.
  7. H. Zhang and E. Sánchez-Sinencio, “Linearization techniques for CMOS low noise amplifiers: a tutorial,” IEEE Transactions on Circuits and Systems I, vol. 58, no. 1, pp. 22–36, 2011. View at: Publisher Site | Google Scholar
  8. Y. Ding and R. Harjani, “A +18 dBm IIP3 LNA in 0.35 μm CMOS,” in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 162–443, February 2001. View at: Google Scholar
  9. E. Keehr and A. Hajimiri, “Equalization of IM3 products in wideband direct-conversion receivers,” in Proceedings of the IEEE International Solid State Circuits Conference (ISSCC'08), pp. 199–607, February 2008. View at: Publisher Site | Google Scholar
  10. Y.-S. Youn, J.-H. Chang, K.-J. Koh, Y.-J. Lee, and H.-K. Yu, “A 2 GHz 16 dBm IIP3 low noise amplifier in 0.25 μm CMOS technology,” in Proceedings of the IEEE International Solid State Circuits Conference (ISSCC'03), pp. 439–507, February 2003. View at: Google Scholar
  11. H. M. Geddada, J. W. Park, and J. Silva-Martinez, “Robust derivative superposition method for linearising broadband LNAs,” Electronics Letters, vol. 45, no. 9, pp. 435–436, 2009. View at: Publisher Site | Google Scholar
  12. T.-S. Kim and B.-S. Kim, “Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker,” IEEE Microwave and Wireless Components Letters, vol. 16, no. 4, pp. 182–184, 2006. View at: Publisher Site | Google Scholar
  13. S. Sesia, M. Baker, and I. Toufik, LTE, The UMTS Long Term Evolution: From Theory to Practice, Wiley, Chichester, UK, 2009.
  14. C. W. Liu and M. Damgaard, “IP2 and IP3 nonlinearity specifications for 3G/WCDMA receivers,” High Frequency Electronics, pp. 16–29, June 2009. View at: Google Scholar
  15. “Avagotech Datasheets,” 2013, View at: Google Scholar
  16. “Analog Devices Datasheets,” 2013, View at: Google Scholar
  17. F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Wide-band CMOS low-noise amplifier exploiting thermal noise canceling,” IEEE Journal of Solid-State Circuits, vol. 39, no. 2, pp. 275–282, 2004. View at: Publisher Site | Google Scholar
  18. C.-F. Liao and S.-I. Liu, “A broadband noise-canceling CMOS LNA for 3.1-10.6 GHz UWB receiver,” in Proceedings of the IEEE Conference on Custom Integrated Circuits, pp. 160–163, September 2005. View at: Publisher Site | Google Scholar
  19. S. Chehrazi, A. Mirzaei, R. Bagheri, and A. A. Abidi, “A 6.5 GHz wideband CMOS low noise amplifier for multi-band use,” in Proceedings of the IEEE Conference on Custom Integrated Circuits, pp. 796–799, September 2005. View at: Publisher Site | Google Scholar
  20. R. Gharpurey, “A broadband low-noise front-end amplifier for Ultra Wideband in 0.13-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1983–1986, 2005. View at: Publisher Site | Google Scholar
  21. S. B. T. Wang, A. M. Niknejad, and R. W. Brodersen, “A sub-mW 960-MHz ultra-wideband CMOS LNA,” in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC'05), pp. 35–38, June 2005. View at: Google Scholar
  22. T. W. Kim and B. Kim, “A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 945–953, 2006. View at: Publisher Site | Google Scholar
  23. J.-H. C. Zhan and S. S. Taylor, “A 5 GHz resistive-feedback CMOS LNA for low-cost multi-standard applications,” in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC'06), pp. 191–200, February 2006. View at: Google Scholar
  24. B. G. Perumana, J.-H. C. Zhan, S. S. Taylor, and J. Laskar, “A 0.5-6 GHz improved linearity, resistive feedback 90-nm CMOS LNA,” in Proceedings of the IEEE Asian Solid-State Circuits Conference (ASSCC'06), pp. 263–266, November 2006. View at: Publisher Site | Google Scholar
  25. R. Bagheri, A. Mirzaei, S. Chehrazi et al., “An 800-MHz-6-GHz software-defined wireless receiver in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2860–2875, 2006. View at: Publisher Site | Google Scholar
  26. M. Vidojkovic, M. Sanduleanu, J. Van Der Tang, P. Baltus, and A. Van Roermund, “A 1.2 V, inductorless, broadband LNA in 90 nm CMOS LP,” in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC'07), pp. 53–56, June 2007. View at: Publisher Site | Google Scholar
  27. W.-H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, “A highly linear broadband CMOS LNA employing noise and distortion cancellation,” in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC'07), pp. 61–64, June 2007. View at: Publisher Site | Google Scholar
  28. M. T. Reiha and J. R. Long, “A 1.2 v reactive-feedback 3.1-10.6 GHz low-noise amplifier in 0.13 μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 5, pp. 1023–1032, 2007. View at: Publisher Site | Google Scholar
  29. R. Ramzan, S. Andersson, J. Dabrowski, and C. Svensson, “A 1.4 V 25 mW inductorless wideband LNA in 0.13 μm CMOS,” in Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC'07), pp. 417–613, February 2007. View at: Publisher Site | Google Scholar
  30. J. Borremans, P. Wambacq, and D. Linten, “An ESD-protected DC-to-6GHz 9.7 mW LNA in 90nm digital CMOS,” in Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC'07), pp. 417–613, February 2007. View at: Publisher Site | Google Scholar
  31. S. C. Blaakmeer, E. A. M. Klumperink, B. Nauta, and D. M. W. Leenaerts, “An inductorless wideband balun-LNA in 65 nm CMOS with balanced output,” in Proceedings of the 33rd European Solid-State Circuits Conference (ESSCIRC'07), pp. 364–367, September 2007. View at: Publisher Site | Google Scholar
  32. S.-S. Song, D.-G. Im, H.-T. Kim, and K. Lee, “A highly linear wideband CMOS low-noise amplifier based on current amplification for digital TV tuner applications,” IEEE Microwave and Wireless Components Letters, vol. 18, no. 2, pp. 118–120, 2008. View at: Publisher Site | Google Scholar
  33. J. Borremans, P. Wambacq, C. Soens, Y. Rolain, and M. Kuijk, “Low-area active-feedback low-noise amplifier design in scaled digital CMOS,” IEEE Journal of Solid-State Circuits, vol. 43, no. 11, pp. 2422–2433, 2008. View at: Publisher Site | Google Scholar
  34. T. Chang, J. Chen, L. Rigge, and J. Lin, “A packaged and ESD-protected inductorless 0.1-8 GHz wideband CMOS LNA,” IEEE Microwave and Wireless Components Letters, vol. 18, no. 6, pp. 416–418, 2008. View at: Publisher Site | Google Scholar
  35. S. Woo, W. Kim, C.-H. Lee, K. Lim, and J. Laskar, “A 3.6 mW differential common-gate CMOS LNA with positive-negative feedback,” in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC'09), pp. 218–219, February 2009. View at: Publisher Site | Google Scholar
  36. M. El-Nozahi, E. Sanchez-Sinencio, and K. Entesari, “A CMOS low-noise amplifier with reconfigurable input matching network,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 5, pp. 1054–1062, 2009. View at: Publisher Site | Google Scholar
  37. D. Im, I. Nam, H.-T. Kim, and K. Lee, “A wideband CMOS Low noise amplifier employing noise and IM2 distortion cancellation for a digital TV tuner,” IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 686–698, 2009. View at: Publisher Site | Google Scholar
  38. W.-H. Chen, Designs of broadband highly linear CMOS LNAs for multiradio multimode applications [Ph.D. thesis], University of California, Berkley, Calif, USA, 2010.
  39. S. K. Hampel, O. Schmitz, M. Tiebout, and I. Rolfes, “Inductorless 1-10.5 GHz wideband LNA for multistandard applications,” in Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC'09), pp. 269–272, November 2009. View at: Publisher Site | Google Scholar
  40. J. Kim, S. Hoyos, and J. Silva-Martinez, “Wideband common-gate CMOS LNA employing dual negative feedback with simultaneous noise, gain, and bandwidth optimization,” IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 9, pp. 2340–2351, 2010. View at: Publisher Site | Google Scholar
  41. D. Im, I. Nam, J.-Y. Choi, B.-K. Kim, and K. Lee, “A CMOS active feedback wideband single-to-differential LNA using inductive shunt-peaking for saw-less SDR receivers,” in Proceedings of the 6th IEEE Asian Solid-State Circuits Conference (A-SSCC'10), pp. 153–156, November 2010. View at: Publisher Site | Google Scholar
  42. H. Wang, L. Zhang, and Z. Yu, “A wideband inductorless LNA with local feedback and noise cancelling for low-power low-voltage applications,” IEEE Transactions on Circuits and Systems I, vol. 57, no. 8, pp. 1993–2005, 2010. View at: Publisher Site | Google Scholar
  43. D. Im, I. Nam, and K. Lee, “A CMOS active feedback balun-LNA with high IIP2 for wideband digital TV receivers,” IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 12, pp. 3566–3579, 2010. View at: Publisher Site | Google Scholar
  44. P.-I. Mak and R. P. Martins, “A 2 × VDD-enabled mobile-TV RF front-end with TV-GSM interoperability in 1-V 90-nm CMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 7, pp. 1664–1676, 2010. View at: Publisher Site | Google Scholar
  45. Y.-H. Yu, Y.-S. Yang, and Y.-J. E. Chen, “A compact wideband CMOS low noise amplifier with gain flatness enhancement,” IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 502–509, 2010. View at: Publisher Site | Google Scholar
  46. M. El-Nozahi, A. A. Helmy, E. Sánchez-Sinencio, and K. Entesari, “An inductor-less noise-cancelling broadband low noise amplifier with composite transistor pair in 90 nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1111–1122, 2011. View at: Publisher Site | Google Scholar
  47. E. A. Sobhy, A. A. Helmy, S. Hoyos, K. Entesari, and E. Sanchez-Sinencio, “A 2.8-mW Sub-2-dB noise-figure inductorless wideband CMOS LNA employing multiple feedback,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 12, pp. 3154–3161, 2011. View at: Publisher Site | Google Scholar
  48. M. Moezzi and M. S. Bakhtiar, “Wideband LNA using active inductor with multiple feed-forward noise reduction paths,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 4, pp. 1069–1078, 2012. View at: Publisher Site | Google Scholar
  49. J. W. Park and B. Razavi, “A harmonic-rejecting CMOS LNA for broadband radios,” IEEE Journal of Solid-State Circuits, vol. 48, no. 4, pp. 1072–1084, 2013. View at: Google Scholar

Copyright © 2014 Grzegorz Szczepkowski and Ronan Farrell. This is an open access distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Related articles

No related content is available yet for this article.
 PDF Download Citation Citation
 Download other formatsMore
 Order printed copiesOrder

Related articles

No related content is available yet for this article.

Article of the Year Award: Outstanding research contributions of 2021, as selected by our Chief Editors. Read the winning articles.