Efficient QCA Exclusive-or and Multiplexer Circuits Based on a Nanoelectronic-Compatible Designing Approach

Table 5

The proposed multiplexer improvements in comparison to other previous designs.

Improvement	Circuit	Gate count; (majority gate + inverter)	Area	Cell count	Latency
2 : 1 multiplexer	[12]	25%	62%	50%	25%
	[13]	25%	50%	36%	25%
	[14]	0%	57%	57%	25%
	[15]	0%	66%	61%	25%
	[16]	0%	57%	59%	25%
	[17]	25%	40%	39%	25%
	[18]	40%	−50%	0%	0%
4 : 1 multiplexer	[19]	40%	56%	66%	−28%
	[20]	50%	56%	33%	12%
	[21]	18%	26%	46%	−42%
	[14]	0%	54%	48%	22%
	[15]	0%	84%	82%	36%
	[16]	18%	56%	61%	−16%
	[22]	35%	−37%	−12%	−75%