Journal of Industrial Engineering / 2013 / Article / Tab 4

Research Article

Chip Attach Scheduling in Semiconductor Assembly

Table 4

Comparison of the total setup time using heuristics and -learning.

Dataset no.WSPTMWSPTRALFM-MWSPTLFM-RALWFQ-learning

10.81330.84970.32830.72310.38840.38951.0000
20.83331.30000.43580.75640.52630.40941.0000
30.87121.16330.42070.63610.49370.42981.0000
41.12800.71230.46290.85160.51390.43181.0000
50.96291.31210.41790.85970.51150.38731.0000
60.74891.03930.41040.74890.45420.40741.0000
71.78682.21820.82231.40691.01250.41741.0000
80.64560.85080.40550.66940.50530.37951.0000
90.92450.99460.50130.78210.66940.41631.0000
101.10251.78750.67031.03710.90790.48941.0000
110.99731.36550.39940.96860.51290.40661.0000
120.79041.11110.44190.61950.50810.42581.0000

Average0.96711.22540.47640.83830.58370.41581.0000