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Journal of Industrial Engineering
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2013
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Article
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Tab 4
Research Article
Chip Attach Scheduling in Semiconductor Assembly
Table 4
Comparison of the total setup time using heuristics and
-learning.
Dataset no.
WSPT
MWSPT
RA
LFM-MWSPT
LFM-RA
LWF
Q
-learning
1
0.8133
0.8497
0.3283
0.7231
0.3884
0.3895
1.0000
2
0.8333
1.3000
0.4358
0.7564
0.5263
0.4094
1.0000
3
0.8712
1.1633
0.4207
0.6361
0.4937
0.4298
1.0000
4
1.1280
0.7123
0.4629
0.8516
0.5139
0.4318
1.0000
5
0.9629
1.3121
0.4179
0.8597
0.5115
0.3873
1.0000
6
0.7489
1.0393
0.4104
0.7489
0.4542
0.4074
1.0000
7
1.7868
2.2182
0.8223
1.4069
1.0125
0.4174
1.0000
8
0.6456
0.8508
0.4055
0.6694
0.5053
0.3795
1.0000
9
0.9245
0.9946
0.5013
0.7821
0.6694
0.4163
1.0000
10
1.1025
1.7875
0.6703
1.0371
0.9079
0.4894
1.0000
11
0.9973
1.3655
0.3994
0.9686
0.5129
0.4066
1.0000
12
0.7904
1.1111
0.4419
0.6195
0.5081
0.4258
1.0000
Average
0.9671
1.2254
0.4764
0.8383
0.5837
0.4158
1.0000