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Journal of Optimization
Volume 2017, Article ID 8624021, 11 pages
https://doi.org/10.1155/2017/8624021
Research Article

Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

1Laboratory of Electronic and Microelectronic, Faculty of Sciences at Monastir, University of Monastir, 5000 Monastir, Tunisia
2Networked Objects Control & Communication Systems Laboratory, National Engineering School of Sousse, BP 264, Sousse Erriadh, 4023 Sousse, Tunisia

Correspondence should be addressed to Siwar Ben Haj Hassine; moc.liamg@enissah.jah.rawis

Received 18 August 2016; Revised 8 January 2017; Accepted 24 January 2017; Published 19 February 2017

Academic Editor: Manlio Gaudioso

Copyright © 2017 Siwar Ben Haj Hassine et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Shortening the marketing cycle of the product and accelerating its development efficiency have become a vital concern in the field of embedded system design. Therefore, hardware/software partitioning has become one of the mainstream technologies of embedded system development since it affects the overall system performance. Given today’s largest requirement for great efficiency necessarily accompanied by high speed, our new algorithm presents the best version that can meet such unpreceded levels. In fact, we describe in this paper an algorithm that is based on HW/SW partitioning which aims to find the best tradeoff between power and latency of a system taking into consideration the dark silicon problem. Moreover, it has been tested and has shown its efficiency compared to other existing heuristic well-known algorithms which are Simulated Annealing, Tabu search, and Genetic algorithms.