Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

Table 7

Design result provided by Simulated Annealing algorithm.

8-point DCT	Best partition	Hardware	14 operations of (×)	4 operations of (+)
		Software	2 operations of (×)	22 operations of (+)
	Total power consumed (mW)		91.55
	The system’s latency (ns)		586
16-point DCT	Best partition	Hardware	60 operations of (×)	48 operations of (+)
		Software	68 operations of (×)	48 operations of (+)
	Total power consumed (mW)		487.78
	The system’s latency (ns)		3024
H.264	Total power consumed (W)		6.250
	The system’s latency (ns)		1740