Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

Table 9

Design result provided by Genetic algorithm.

8-point DCT	Best partition	Hardware	12 operations of (×)	22 operations of (+)
		Software	4 operations of (×)	4 operations of (+)
	Total power consumed (mW)		84.4
	The system’s latency (ns)		630
16-point DCT	Best partition	Hardware	60 operations of (×)	90 operations of (+)
		Software	68 operations of (×)	6 operations of (+)
	Total power consumed (mW)		501.652
	The system’s latency (ns)		2896
H.264	Total power consumed (W)		6.050
	The system’s latency (ns)		1650