Table of Contents
Research Letters in Physics
Volume 2008, Article ID 286546, 5 pages
Research Letter

Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

1Unité de Recherche de Physique des Solides, Département de Physique, Faculté des Sciences de Monastir, Monastir 5019, Tunisia
2Laboratoire de Physique de La Matière, UMR-CNRS 5511, INSA De Lyon, Bâtement 502, 20 Avenue Albert Einstein, Villeurbanne Cedex 69621, France

Received 10 October 2007; Accepted 8 January 2008

Academic Editor: Anil R. Chourasia

Copyright © 2008 A. Bouazra et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.