Robert W. Dutton, Edwin C. Kan, "Hierarchical Process Simulation for Nano-Electronics", VLSI Design, vol. 6, Article ID 019402, 7 pages, 1998. https://doi.org/10.1155/1998/19402
Hierarchical Process Simulation for Nano-Electronics
The challenges of computational electronics are considered from the perspective of process simulation. Essential limitations for device scaling posed from a technology point of view are discussed along with many new research opportunities. The key areas considered include: bulk processing, interconnect technology and software engineering for computational electronics.
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