VLSI Design

VLSI Design / 1998 / Article
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VLSI Design On Self-Checking Systems

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Volume 5 |Article ID 024951 | https://doi.org/10.1155/1998/24951

Yeong-Ruey Shieh, Cheng-Wen Wu, "Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults", VLSI Design, vol. 5, Article ID 024951, 16 pages, 1998. https://doi.org/10.1155/1998/24951

Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults

Abstract

We present in this paper an approach to designing partially strongly code-disjoint (PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in addition to gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only a small number of extra transistors for monitoring abnormal static currents, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry not only can detect the faults in the functional circuit but also can detect or tolerate faults in itself, making it a good candidate for checker design. Switch and circuit level simulations were performed on a sample circuit, and a sample 4-out-of-8 code checker chip using the proposed technique has been designed, fabricated, and tested, showing the correctness of the method. Performance penalty is reduced by a novel BiCMOS checker circuit.

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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