VLSI Design

VLSI Design / 1998 / Article

Open Access

Volume 7 |Article ID 032654 | https://doi.org/10.1155/1998/32654

C. P. Ravikumar, H. Joshi, "SCOAP-based Testability Analysis from Hierarchical Netlists", VLSI Design, vol. 7, Article ID 032654, 11 pages, 1998. https://doi.org/10.1155/1998/32654

SCOAP-based Testability Analysis from Hierarchical Netlists

Received27 Jul 1995


Circuits of VLSI complexity are designed using modules such as adders, multipliers, register files, memories, multiplexers, and busses. During the high-level design of such a circuit, it is important to be able to consider several alternative designs and compare them on counts of area, performance, and testability. While tools exist for area and delay estimation of module-level circuits, most of the testability analysis tools work on gate-level descriptions of the circuit. Thus an expensive operation of flattening the circuit becomes necessary to carry out testability analysis. In this paper, we describe a time and space-efficient technique for evaluating the well known SCOAP testability measure of a circuit from its hierarchical description with two or more levels of hierarchy. We introduce the notion of SCOAP Expression Diagrams for functional modules, which can be precomputed and stored as part of the module data base. Our hierarchical testability analysis program, HISCOAP, reads the SCOAP expression diagrams for the modules used in the circuit, and evaluates the SCOAP measure in a systematic manner. The program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential. We show that our algorithm also has a straightforward parallel realization.

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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