VLSI Design

VLSI Design / 1998 / Article

Open Access

Volume 7 |Article ID 037237 | https://doi.org/10.1155/1998/37237

Fadi Busaba, Parag K. Lala, Alvernon Walker, "On Self-Checking Design of CMOS Circuits for Multiple Faults", VLSI Design, vol. 7, Article ID 037237, 11 pages, 1998. https://doi.org/10.1155/1998/37237

On Self-Checking Design of CMOS Circuits for Multiple Faults

Received28 Jun 1995
Accepted10 Oct 1995


A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experiemntal results show the overhead, delay and power consumption for the proposed technique. This paper also presents a technique for designing multistage TSC FCMOS circuits.

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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