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VLSI Design
Volume 6 (1998), Issue 1-4, Pages 223-237

Recent Advances in Device Simulation Using Standard Transport Models

1Dipartimento di Elettronica, Informatica e Sistemistica, Università di Bologna, Viale Risorgimento, Bologna 2 - 40136, Italy
2NVM Process Development, SGS-Thomson Microelectronics, Via Olivetti, Agrate Brianza 2 - 20041, Italy

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper we address a number of issues related with device simulation in 3-D, and point out a few deficiencies which still prevent 3-D device simulation to be widely accepted as a standard tool for device design and optimization in an engineering environment. More specifically, such deficiencies have to do with structure definition and mesh generation, as well as with the computational burden which is typically associated with discretization meshes featuring 50.000 nodes or more. Next, we address the problem of validating advanced physical models in 3-D by means of our device simulator HFIELDS-3D and use a flash-EEPROM cell manufactured at ST-Microelectronics as a test vehicle for the validation of hot-carrier injection into the floating gate and Fowler-Nordheim tunneling across the gate oxide.