We consider the problem of selecting the proper implementation of each circuit module from a cell library to minimize the propagation delay along every path from any primary input to any primary output subject to an upper bound on the total area of the circuit. Different module implementations may have different areas and delays on the paths. Wc show that the latter problem is NP-hard even for directed acyclic graphs with two implementations per module and no restrictions on the overall area of the circuit. Wc present a novel retiming based heuristic for determining the minimum clock period on sequential circuits. Although our heuristics may handle a bound on the total area of the circuit, emphasis is given on the timing issue.