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VLSI Design
Volume 6 (1998), Issue 1-4, Pages 35-38

Simulation of a Single Electron Tunnel Transistor with Inclusion of Inelastic Macroscopic Quantum Tunneling of Charge

Institute for Microelectronics, TU Vienna, Gusshausstrasse 27-29, Vienna A-1040, Austria

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • M Forshaw, R Stadler, D Crawley, and K Nikoli, “A short review of nanoelectronic architectures,” Nanotechnology, vol. 15, no. 4, pp. S220–S223, 2004. View at Publisher ยท View at Google Scholar