In FPGAs the routing resources are fixed and their usage is constrained by the location of antifuses. In addition, the antifuses affect the layout performance significantly, depending on the technology. Hence, simplistic placement level assumptions turn out to be grossly inadequate in predicting the timing and wirability behavior of a layout. There is a need, therefore, for a layout technique which changes the layout at placement level based on accurate post-layout timing analysis and net wirability. In this paper we consider such a wirability and performance driven layout flow for row-based FPGAs. Timing information from a post-layout timing analyzer and wirability information from global and channel routers are used by an incremental placer to effectively perturb the placement. A large improvement (up to 29%) in timing, has been obtained (compared to non-iterative FPGA layout) for a set of industrial designs and benchmark examples.