Abstract
Fault sets that accurately describe physical failures are required for efficient pattern generation and fault coverage evaluation. The fault model presented in this paper uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including bridging faults that connect more than two nets, break faults that break a net into more than two parts, and compound faults. The developed analysis method extracts the comprehensive set of realistic faults from the layout of CMOS ICs and for each fault computes the probability of occurrence. The results obtained by the tool REFLEX show that bridging faults connecting more than two nets account for a significant portion of all faults and cannot be neglected.