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VLSI Design
Volume 6 (1998), Issue 1-4, Pages 321-329

Modeling Nonlinear and Chaotic Dynamics in Semiconductor Device Structures

Institut für Theoretische Physik, Technische Universität Berlin, Hardenbergstraβe 36, Berlin 10623, Germany

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We review the modeling and simulation of electrical transport instabilities in semiconductors with a special emphasis on recent progress in the application to semiconductor microstructures. The following models are treated in detail: (i) The dynamics of current filaments in the regime of low-temperature impurity breakdown is studied. In particular we perform 2D simulations of the nascence of a filament upon application of a bias voltage. (ii) Vertical electrical transport in layered semiconductor structures like the heterostructure hot electron diode is considered. Periodic as well as chaotic spatio-temporal spiking of the current is obtained. In particular we find long transients of spatio-temporal chaos preceding regular spiking.