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VLSI Design
Volume 7 (1998), Issue 4, Pages 321-336

A High Level Synthesis System for VLSI Image Processing Applications

1ETCA Système de Perception Laboratory, 16 bis Avenue Prieur de la Côte d’Or, Arceuil, F-94114, France
2lnstitut d’Electronique Fondamentale, University of Paris-XI, Orsay, F-91405, France

Received 19 August 1994; Accepted 10 March 1995

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We present a VLSI synthesis environment dedicated to the design of image processing architectures. The environment includes a “front-end” data-flow emulator for validation of the algorithms and the RTL-synthesis system called ALPHA. The latter implements a stochastic search in the design space and produces efficient solutions considering the “restricted” domain of concerned applications. Two simulated Annealing (SA) algorithms run in sequence for data-path synthesis (scheduling and module selection) and then for control synthesis and data-path completion (binding). An interesting feature of the first optimization is the use of the data-flow graph regularity to predict the control influence in terms of the future design. A few designs have already been compiled under this environment including a default detector presented here.