Table of Contents
VLSI Design
Volume 9, Issue 3, Pages 219-235

Scalability Analysis for Conservative Simulation of Logical Circuits

1FB Informatik, Fern Universität-GHS Hagen, Postfach 940, LG Technische Informatik II, Hagen 58084, Germany
2Institut für Informatik, Universität Halle-Wittenberg, Halle (Saale) 06099, Germany
3Telekom Entwicklungszentrum Südwest, Neugrabenweg 4, Saarbücken 66123, Germany

Received 26 May 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by partitioning strategies. To incorporate overhead due to the management of data structures, we use a simulation on an ideal parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM prototype, yielding both an implementation and a basis for data structure optimizations. One of the major tools to achieve these optimizations is the SB-PRAM's hardware support for parallel prefix operations. Our reimplementation of the PTHOR program on the SB-PRAM yields substantially higher speedups than before.