Table of Contents
VLSI Design
Volume 9, Issue 3, Pages 219-235
http://dx.doi.org/10.1155/1999/14802

Scalability Analysis for Conservative Simulation of Logical Circuits

1FB Informatik, Fern Universität-GHS Hagen, Postfach 940, LG Technische Informatik II, Hagen 58084, Germany
2Institut für Informatik, Universität Halle-Wittenberg, Halle (Saale) 06099, Germany
3Telekom Entwicklungszentrum Südwest, Neugrabenweg 4, Saarbücken 66123, Germany

Received 26 May 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Jörg Keller, Thomas Rauber, and Bernd Rederlechner, “Scalability Analysis for Conservative Simulation of Logical Circuits,” VLSI Design, vol. 9, no. 3, pp. 219-235, 1999. https://doi.org/10.1155/1999/14802.