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VLSI Design
Volume 10, Issue 2, Pages 177-202
http://dx.doi.org/10.1155/1999/16415

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

VLSI Design Laboratory, Department of Electrical and Computer Engineering, University of Patras, Rio 26500, Greece

Received 13 April 1998; Accepted 21 June 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

K. Masselos, P. Merakos, T. Stouraitis, and C. E. Goutis, “Computation Reordering: A Novel Transformation for Low Power DSP Synthesis,” VLSI Design, vol. 10, no. 2, pp. 177-202, 1999. https://doi.org/10.1155/1999/16415.