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VLSI Design
Volume 10 (1999), Issue 2, Pages 217-235

Principles for Language Extensions to VHDL to Support High-Level Modeling

1Dept. of Computer Science, The University of Adelaide, Adelaide 5005, SA, Australia
2Dept. of ECECS, PO Box 210030, University of Cincinnati, Cincinnati 45221-0030, OH, USA

Received 9 November 1997; Accepted 22 March 1999

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper reviews proposals for extensions to VHDL to support high-level modeling and places them within a taxonomy that describes the modeling requirements they address. Many of the proposals focus on object-oriented extensions, whereas this paper argues that extension of VHDL to support high-level modeling requires a broader review. The paper presents a detailed discussion of issues to be considered in adding high-level modeling extensions to VHDL, including concurrency and communication, abstraction using entity interfaces, object-oriented data modeling, encapsulation, signal assignment semantics, shared variables, multiple inheritance, genericity and synthesis. Emphasis is placed on the importance of designing simple orthogonal semantic mechanisms that interact in well defined ways, and that integrate cleanly with existing language features.