The use is made of the BJT transit frequency limit (fTL) dependence on the MOSFET parameters (L, Vth) to design BiCMOS digital circuits. The fTL relation is used in conjunction with the established BiCMOS gate delay models. It is shown that the minimum delay BiCMOS circuits driving the large capacitive load, can be designed at the transit frequency limit with the reduced BJT AREA factor. The time delay calculations are presented for a typical BiCMOS circuit and comparison is made with the results simulated using SPICE.