A VLSI Design for Implementation of Transform Domain Adaptive Filters
A VLSI implementation of a dedicated digital signal processor is presented. The processor is tailored for efficient implementation of transform domain adaptive filters. It incorporates a butterfly processor which performs butterfly operation to implement the required transformation. It is also able to perform complex addition, subtraction and multiplication. The butterfly processor makes use of a redundant binary tree multiplier with a recently proposed coding of signed-digit numbers which reduces the number of levels in the tree by one. An on-chip read only memory holds the transformation coefficients. The contents of the ROM determine the type of transform. The processor incorporates an ALU to perform integer arithmetic, address calculations and implementation of circular memory scheme. For fastest accessibility, the essential variables of the algorithm are implemented in a register fire.
Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.