VLSI Design

VLSI Design / 1999 / Article

Open Access

Volume 9 |Article ID 091893 | https://doi.org/10.1155/1999/91893

G. Theodoridis, S. Theoharis, D. Soudris, C. Goutis, "A New Method for Low Power Design of Two-Level Logic Circuits", VLSI Design, vol. 9, Article ID 091893, 11 pages, 1999. https://doi.org/10.1155/1999/91893

A New Method for Low Power Design of Two-Level Logic Circuits

Received24 Mar 1997
Accepted18 Jan 1998

Abstract

A new method for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by adding extra input signals to specific gates. Employing the statistic properties of the primary inputs, a new concept for grouping the input variables with similar features is introduced. Appropriate input variables are chosen for reducing the switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm, which generates the set of all groups of the variables and solves the minimum covering problem for each group is developed. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a substantial power reduction can be achieved.

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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