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VLSI Design
Volume 9 (1999), Issue 2, Pages 147-157

A New Method for Low Power Design of Two-Level Logic Circuits

1VLSI Design Laboratory, Dept. of Electrical and Computer Engineering, University of Patras, Rio 26 110, Greece
2VLSI Design and Testing Center, Laboratory of Electrical & Electronic Materials Technology, Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi 67 100, Greece

Received 24 March 1997; Accepted 18 January 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A new method for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by adding extra input signals to specific gates. Employing the statistic properties of the primary inputs, a new concept for grouping the input variables with similar features is introduced. Appropriate input variables are chosen for reducing the switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm, which generates the set of all groups of the variables and solves the minimum covering problem for each group is developed. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a substantial power reduction can be achieved.