Table of Contents
VLSI Design
Volume 15, Issue 3, Pages 557-562

Timing Challenges for Very Deep Sub-Micron (VDSM) IC

1Baynacre, Inc., 1733 Red Maple St., Union City 94587, CA, USA
2Department of Electrical Engineering, Wright State University, Dayton 45435, OH, USA

Received 15 March 2001; Revised 30 January 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Many IC design houses failed to be market leaders because they miss the market window due to timing closure problems. Compared to half-micron designs, the amount of time spent on timing verification has greatly increased. Cell delays can be accurately estimated during logic synthesis. However, interconnect delays are unknown until the wire geometry is defined in physical design. Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately. Delay estimates for individual nets (global nets, long wires, large fan-outs, buses), which matter most for the critical paths can be inaccurate and cause a design failure. Inaccurate timing verification causes silicon failure in shipped products that results in the loss of millions of dollars spent designing a high-performance product and potentially larger costs due to lost market share. Full-chip, sign-off verification with silicon-accuracy will allow these problems to be discovered and fixed before tape-out.