Abstract
Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. The impact of this switching on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach has been shown to be overly pessimistic in some cases, while somewhat optimistic in others. Apart from the delay modeling inaccuracies, the temporal and functional isolation of the aggressors can contribute to the pessimism. This paper introduces TACO, a timing analysis approach that addresses both these issues. TACO captures the provably worst-and best-case delays as a function of the timing-window inputs to the gates. We then present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. Results on industrial examples and benchmark circuits show the value of our approach.