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VLSI Design
Volume 15, Issue 3, Pages 619-628
http://dx.doi.org/10.1080/1065514021000012237

CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization

1Agere Systems, 7777 Center Avenue #300, Huntington Beach 92647, CA, USA
2Electrical Department, Arizona State University, Tempe 85287-5706, AZ, USA

Received 15 March 2001; Revised 30 January 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Sangho Lee and Edwin W. Greeneich, “CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization,” VLSI Design, vol. 15, no. 3, pp. 619-628, 2002. https://doi.org/10.1080/1065514021000012237.